公开(公告)号：US09413309B1

公开(公告)日：2016-08-09

申请号：US14668832

申请日：2015-03-25

Applicant: Analog Devices Global

Inventor： Dixian Zhao ,  Patrick Reynaert ,  Michael F. Keaveney

IPC: H03F3/45 ,  H03F3/193 ,  H03F1/02

CPC classification number: H03F3/193 ,  H03F1/0233 ,  H03F3/45188 ,  H03F2200/451 ,  H03F2203/45024 ,  H03F2203/45481

Abstract: Provided herein are apparatus and methods for a cascode amplifier topology for millimeter-wave power application. The cascode amplifier can use a neutralized common source stage cascoded with a bootstrapped common gate stage to provide an amplifier topology having enhanced performance, gain, stability and reliability. Additionally, a bootstrap capacitor of the common gate stage can be patterned between the source fingers and the drain fingers of a cascode transistor so as to improve device performance. Operating as an RF power amplifier, a single-stage cascode amplifier using the neutralized common source stage with the bootstrapped common gate stage can provide greater than 15 dB of power gain to signals of the E band.

Abstract translation: 本文提供了用于毫米波功率应用的共源共栅放大器拓扑的装置和方法。 共源共栅放大器可以使用与自举公共栅极级级联的中和的共源电源级，以提供具有增强的性能，增益，稳定性和可靠性的放大器拓扑。 此外，可以在共源栅极晶体管的源极指和漏极指之间图案化公共栅极级的自举电容器，以便提高器件性能。 作为RF功率放大器，使用具有自举公共栅极级的中和的共源极级的单级共源共栅放大器可以向E波段的信号提供大于15dB的功率增益。

公开(公告)号：US09503109B2

公开(公告)日：2016-11-22

申请号：US14726913

申请日：2015-06-01

Applicant: ANALOG DEVICES GLOBAL

Inventor： David J. McLaurin ,  Christopher W. Angell ,  Michael F. Keaveney

IPC: H03K3/013 ,  H03L7/081 ,  H03L7/197 ,  H03L7/085 ,  H03L7/10 ,  H03L7/199 ,  H03L7/23

CPC classification number: H03L7/1976 ,  H03L7/085 ,  H03L7/104 ,  H03L7/199 ,  H03L7/23

Abstract: Apparatus and methods for synchronizing phase-locked loops (PLLs) are provided. In certain implementations, a fractional-N synthesizer includes a PLL and a control circuit that controls a division value of the PLL. The control circuit includes an interpolator, a reset phase adjustment calculator, and a synchronization circuit. The interpolator can control a fractional portion of the PLL's division value. The reset phase adjustment calculator can include a counter for counting a number of cycles of the reference clock signal since initialization of the fractional-N synthesizer, and the reset phase adjustment calculator can generate a phase adjustment signal based on the count. The synchronization circuit can synchronize the PLL in response to a synchronization signal, and can correct for a synchronization phase error indicated by the phase adjustment signal.

公开(公告)号：US09484935B2

公开(公告)日：2016-11-01

申请号：US14134767

申请日：2013-12-19

Applicant: ANALOG DEVICES GLOBAL

Inventor： Hyman Shanan ,  Michael F. Keaveney

IPC: H03L7/06 ,  H03L7/099 ,  H03L1/02 ,  H03L7/10

CPC classification number: H03L7/099 ,  H03L1/026 ,  H03L7/104

Abstract: Apparatus and methods for frequency lock enhancement of phase-locked loops (PLLs) are provided. In one aspect, a PLL can include a VCO having a tuning voltage input and a frequency tuning circuit configured to set a frequency band setting of the VCO. The frequency tuning circuit can include a voltage monitor configured to compare the voltage level of the tuning voltage input to one or more tuning voltage threshold levels, a control circuit configured to control at least a frequency band setting and a bias current setting of the VCO, and an amplitude detection circuit configured to compare an amplitude of an oscillation signal of the VCO to one or more amplitude threshold levels.

Abstract translation: 提供了锁相环（PLL）的频率锁定增强的装置和方法。 在一个方面，PLL可以包括具有调谐电压输入的VCO和被配置为设置VCO的频带设置的频率调谐电路。 频率调谐电路可以包括电压监视器，其被配置为将调谐电压输入的电压电平与一个或多个调谐电压阈值电平进行比较，控制电路被配置为至少控制VCO的频带设置和偏置电流设置， 以及振幅检测电路，被配置为将VCO的振荡信号的振幅与一个或多个振幅阈值电平进行比较。

公开(公告)号：US10128894B1

公开(公告)日：2018-11-13

申请号：US15590903

申请日：2017-05-09

Applicant: Analog Devices Global

Inventor： Michael W. O'Brien ,  Michael F. Keaveney ,  Emil Ivanov Entchev ,  James Breslin

IPC: H04B17/21 ,  H04B17/14 ,  H04B1/403 ,  H04B17/12

CPC classification number: H04B1/403 ,  H04B17/11 ,  H04B17/12 ,  H04B17/14 ,  H04B17/18 ,  H04B17/21

Abstract: Aspects of this disclosure relate to active antenna calibration. In some embodiments, a local oscillator signal can be injected into the receive path for misalignment measurement and calibration of the receive path, a transmit signal from a transmit path can be coupled to a receive path, and the transmit path can be calibrated relative to the receive path.

公开(公告)号：US09413366B2

公开(公告)日：2016-08-09

申请号：US14134782

申请日：2013-12-19

Applicant: ANALOG DEVICES GLOBAL

Inventor： Hyman Shanan ,  Michael F. Keaveney

IPC: H03L7/06 ,  H03L7/099 ,  H03L7/085

CPC classification number: H03L7/099 ,  H03L1/026 ,  H03L7/085 ,  H03L7/104

Abstract: Apparatus and methods for frequency lock enhancement of phase-locked loops (PLLs) are provided. In one aspect, a PLL can include a VCO and a calibration voltage generation circuit that can generate a calibration voltage for controlling a tuning voltage input of the VCO when the VCO is being coarsely tuned. Additionally, the calibration voltage generation circuit can sense a temperature of the PLL, and can control a voltage level of the calibration voltage to provide compensation based on the sensed temperature. The calibration voltage generation circuit can include a bandgap reference circuit configured to generate a zero-to-absolute-temperature (ZTAT) current and a proportional-to-absolute temperature (PTAT) current, and the calibration voltage can be generated based in part on a difference between the PTAT current and the ZTAT current.

Abstract translation: 提供了锁相环（PLL）的频率锁定增强的装置和方法。 在一个方面，PLL可以包括VCO和校准电压产生电路，当VCO被粗调谐时，可以产生用于控制VCO的调谐电压输入的校准电压。 此外，校准电压产生电路可以感测PLL的温度，并且可以控制校准电压的电压电平，以基于感测的温度提供补偿。 校准电压产生电路可以包括被配置为产生零绝对温度（ZTAT）电流和比例绝对温度（PTAT）电流的带隙基准电路，并且校准电压可以部分地基于 PTAT电流和ZTAT电流之间的差异。

公开(公告)号：US20150263742A1

公开(公告)日：2015-09-17

申请号：US14726913

申请日：2015-06-01

Applicant: ANALOG DEVICES GLOBAL

Inventor： David J. McLaurin ,  Christopher W. Angell ,  Michael F. Keaveney

IPC: H03L7/197 ,  H03L7/199

CPC classification number: H03L7/1976 ,  H03L7/085 ,  H03L7/104 ,  H03L7/199 ,  H03L7/23

Abstract: Apparatus and methods for synchronizing phase-locked loops (PLLs) are provided. In certain implementations, a fractional-N synthesizer includes a PLL and a control circuit that controls a division value of the PLL. The control circuit includes an interpolator, a reset phase adjustment calculator, and a synchronization circuit. The interpolator can control a fractional portion of the PLL's division value. The reset phase adjustment calculator can include a counter for counting a number of cycles of the reference clock signal since initialization of the fractional-N synthesizer, and the reset phase adjustment calculator can generate a phase adjustment signal based on the count. The synchronization circuit can synchronize the PLL in response to a synchronization signal, and can correct for a synchronization phase error indicated by the phase adjustment signal.

Abstract translation: 提供了用于同步锁相环（PLL）的装置和方法。 在某些实现中，分数N合成器包括PLL和控制PLL的分频值的控制电路。 控制电路包括内插器，复位相位调整计算器和同步电路。 内插器可以控制PLL分频值的小数部分。 复位相位调整计算器可以包括一个计数器，用于对分数N合成器的初始化后的参考时钟信号的周期数进行计数，并且复位相位调整计算器可以基于计数产生相位调整信号。 同步电路可以响应于同步信号来同步PLL，并且可以校正由相位调整信号指示的同步相位误差。

公开(公告)号：US20180331712A1

公开(公告)日：2018-11-15

申请号：US15590903

申请日：2017-05-09

Applicant: Analog Devices Global

Inventor： Michael W. O'Brien ,  Michael F. Keaveney ,  Emil Ivanov Entchev ,  James Breslin

IPC: H04B1/403 ,  H04B17/12 ,  H04B17/21

CPC classification number: H04B1/403 ,  H04B17/11 ,  H04B17/12 ,  H04B17/14 ,  H04B17/18 ,  H04B17/21

Abstract: Aspects of this disclosure relate to active antenna calibration. In some embodiments, a local oscillator signal can be injected into the receive path for misalignment measurement and calibration of the receive path, a transmit signal from a transmit path can be coupled to a receive path, and the transmit path can be calibrated relative to the receive path.