Invention Grant
US09489314B2 Multi-master cache coherent speculation aware memory controller with advanced arbitration, virtualization and EDC
有权
具有高级仲裁，虚拟化和EDC功能的多主缓存一致性揣测内存控制器
- Patent Title: Multi-master cache coherent speculation aware memory controller with advanced arbitration, virtualization and EDC
- Patent Title (中): 具有高级仲裁，虚拟化和EDC功能的多主缓存一致性揣测内存控制器
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Application No.: US14061965Application Date: 2013-10-24
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Publication No.: US09489314B2Publication Date: 2016-11-08
- Inventor: Kai Chirca , Matthew D. Pierson , Timothy D. Anderson
- Applicant: Texas Instruments Incorporated
- Applicant Address: US TX Dallas
- Assignee: TEXAS INSTRUMENTS INCORPORATED
- Current Assignee: TEXAS INSTRUMENTS INCORPORATED
- Current Assignee Address: US TX Dallas
- Agent Robert D. Marshall, Jr.; Frank D. Cimino
- Main IPC: G06F13/00
- IPC: G06F13/00 ; G06F12/10 ; G06F12/08 ; G06F13/16 ; H04L29/06 ; G06F13/42 ; G06F13/28 ; G06F13/40
Abstract:
This invention is an integrated memory controller/interconnect that provides very high bandwidth access to both on-chip memory and externally connected off-chip memory. This invention includes an arbitration for all memory endpoints including priority, fairness, and starvation bounds; virtualization; and error detection and correction hardware to protect the on-chip SRAM banks including automated scrubbing.
Public/Granted literature
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