Invention Grant
- Patent Title: Reducing latency of unified memory transactions
- Patent Title (中): 减少统一内存事务的延迟
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Application No.: US14317308Application Date: 2014-06-27
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Publication No.: US09489322B2Publication Date: 2016-11-08
- Inventor: Mahesh Wagh , Prashanth Kalluraya
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Trop, Pruner & Hu, P.C.
- Main IPC: H03M13/00
- IPC: H03M13/00 ; G06F13/16 ; G06F13/42 ; H04L1/18

Abstract:
In an embodiment, an apparatus includes a consuming logic to request and process data including a critical data portion and a second data portion, the data stored in a memory coupled to a processor interposed between the apparatus and the memory. In addition, the apparatus includes a protocol stack logic coupled to the consuming logic to issue a read request to the memory via the processor to request the data and to receive a plurality of completions responsive to the read request. In an embodiment, the protocol stack logic includes a completion handling logic to send data of a first of the completions to the consuming logic before protocol stack processing is completed on the completions. Other embodiments are described and claimed.
Public/Granted literature
- US20150067433A1 Reducing Latency OF Unified Memory Transactions Public/Granted day:2015-03-05
Information query
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