Invention Grant
- Patent Title: Boolean logic in a state machine lattice
-
Application No.: US14832543Application Date: 2015-08-21
-
Publication No.: US09509312B2Publication Date: 2016-11-29
- Inventor: Harold B Noyes , David R. Brown , Paul Glendenning , Irene Junjuan Xu
- Applicant: Micron Technology, Inc.
- Applicant Address: US ID Boise
- Assignee: Micron Technology, Inc.
- Current Assignee: Micron Technology, Inc.
- Current Assignee Address: US ID Boise
- Agency: Fletcher Yoder, P.C.
- Main IPC: H03K19/177
- IPC: H03K19/177 ; H03K19/20 ; G05B19/045 ; G06F9/44 ; G06F17/50 ; H03K19/0175 ; G06F7/00

Abstract:
Disclosed are methods and devices, among which is a device that includes a finite state machine lattice. The lattice may includes a programmable Boolean logic cell that may be programmed to perform various logic functions on a data stream. The programmability includes an inversion of a first input to the Boolean logic cell, an inversion of a last output of the Boolean logic cell, and a selection of an AND gate or an OR gate as a final output of the Boolean logic cell. The Boolean logic cell also includes end of data circuitry configured to cause the Boolean logic cell to only output after an end of data signifying the end of a data stream is received at the Boolean logic cell.
Public/Granted literature
- US20150365091A1 BOOLEAN LOGIC IN A STATE MACHINE LATTICE Public/Granted day:2015-12-17
Information query
IPC分类: