中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

8 records (took 0.014 seconds)

    BOOLEAN LOGIC IN A STATE MACHINE LATTICE
    1.
    发明申请
    BOOLEAN LOGIC IN A STATE MACHINE LATTICE 有权
    BOOLEAN逻辑在一个状态机床

    公开(公告)号：US20140077838A1

    公开(公告)日：2014-03-20

    申请号：US14087973

    申请日：2013-11-22

    Applicant: Micron Technology, Inc.

    Inventor： Harold B. Noyes ,  David R. Brown ,  Paul Glendenning ,  Irene Junjuan Xu

    IPC: H03K19/20

    CPC classification number: H03K19/17708 ,  G05B19/045 ,  G06F7/00 ,  G06F9/4498 ,  G06F17/5054 ,  H03K19/0175 ,  H03K19/17704 ,  H03K19/20 ,  H03K19/21 ,  Y02T10/82

    Abstract: Disclosed are methods and devices, among which is a device that includes a finite state machine lattice. The lattice may includes a programmable Boolean logic cell that may be programmed to perform various logic functions on a data stream. The programmability includes an inversion of a first input to the Boolean logic cell, an inversion of a last output of the Boolean logic cell, and a selection of an AND gate or an OR gate as a final output of the Boolean logic cell. The Boolean logic cell also includes end of data circuitry configured to cause the Boolean logic cell to only output after an end of data signifying the end of a data stream is received at the Boolean logic cell.

    Abstract translation: 公开了方法和装置，其中包括有限状态机格的装置。 晶格可以包括可编程布尔逻辑单元，其可以被编程为在数据流上执行各种逻辑功能。 可编程性包括对布尔逻辑单元的第一输入的反转，布尔逻辑单元的最后输出的反转，以及选择与门或或门作为布尔逻辑单元的最终输出。 布尔逻辑单元还包括数据电路的结尾，该数据电路被配置为仅在布尔逻辑单元接收到表示数据流结束的数据结束后才输出布尔逻辑单元。

    BOOLEAN LOGIC IN A STATE MACHINE LATTICE
    5.
    发明申请
    BOOLEAN LOGIC IN A STATE MACHINE LATTICE 有权
    BOOLEAN逻辑在一个状态机床

    公开(公告)号：US20150365091A1

    公开(公告)日：2015-12-17

    申请号：US14832543

    申请日：2015-08-21

    Applicant: Micron Technology, Inc.

    Inventor： Harold B. Noyes ,  David R. Brown ,  Paul Glendenning ,  Irene Junjuan Xu

    IPC: H03K19/177 ,  G05B19/045

    CPC classification number: H03K19/17708 ,  G05B19/045 ,  G06F7/00 ,  G06F9/4498 ,  G06F17/5054 ,  H03K19/0175 ,  H03K19/17704 ,  H03K19/20 ,  H03K19/21 ,  Y02T10/82

    Abstract: Disclosed are methods and devices, among which is a device that includes a finite state machine lattice. The lattice may includes a programmable Boolean logic cell that may be programmed to perform various logic functions on a data stream. The programmability includes an inversion of a first input to the Boolean logic cell, an inversion of a last output of the Boolean logic cell, and a selection of an AND gate or an OR gate as a final output of the Boolean logic cell. The Boolean logic cell also includes end of data circuitry configured to cause the Boolean logic cell to only output after an end of data signifying the end of a data stream is received at the Boolean logic cell.

    Abstract translation: 公开了方法和装置，其中包括有限状态机格的装置。 晶格可以包括可编程布尔逻辑单元，其可以被编程为在数据流上执行各种逻辑功能。 可编程性包括对布尔逻辑单元的第一输入的反转，布尔逻辑单元的最后输出的反转，以及选择与门或或门作为布尔逻辑单元的最终输出。 布尔逻辑单元还包括数据电路的结尾，该数据电路被配置为仅在布尔逻辑单元接收到表示数据流结束的数据结束后才输出布尔逻辑单元。

    Boolean logic in a state machine lattice
    7.
    发明授权
    Boolean logic in a state machine lattice 有权
    状态机格子中的布尔逻辑

    公开(公告)号：US09118327B2

    公开(公告)日：2015-08-25

    申请号：US14087973

    申请日：2013-11-22

    Applicant: Micron Technology, Inc.

    Inventor： Harold B Noyes ,  David R. Brown ,  Paul Glendenning ,  Irene Junjuan Xu

    IPC: G05B19/045 ,  G06F7/00 ,  G06F3/037 ,  H03K19/0175 ,  H03K19/20 ,  G06F17/50

    CPC classification number: H03K19/17708 ,  G05B19/045 ,  G06F7/00 ,  G06F9/4498 ,  G06F17/5054 ,  H03K19/0175 ,  H03K19/17704 ,  H03K19/20 ,  H03K19/21 ,  Y02T10/82

    Abstract: Disclosed are methods and devices, among which is a device that includes a finite state machine lattice. The lattice may includes a programmable Boolean logic cell that may be programmed to perform various logic functions on a data stream. The programmability includes an inversion of a first input to the Boolean logic cell, an inversion of a last output of the Boolean logic cell, and a selection of an AND gate or an OR gate as a final output of the Boolean logic cell. The Boolean logic cell also includes end of data circuitry configured to cause the Boolean logic cell to only output after an end of data signifying the end of a data stream is received at the Boolean logic cell.

    Abstract translation: 公开了方法和装置，其中包括有限状态机格的装置。 晶格可以包括可编程布尔逻辑单元，其可以被编程为在数据流上执行各种逻辑功能。 可编程性包括对布尔逻辑单元的第一输入的反转，布尔逻辑单元的最后输出的反转，以及选择与门或或门作为布尔逻辑单元的最终输出。 布尔逻辑单元还包括数据电路的结尾，该数据电路被配置为仅在布尔逻辑单元接收到表示数据流结束的数据结束后才输出布尔逻辑单元。

    METHODS AND SYSTEMS FOR ROUTING IN A STATE MACHINE
    8.
    发明申请
    METHODS AND SYSTEMS FOR ROUTING IN A STATE MACHINE 有权
    用于在状态机中路由的方法和系统

    公开(公告)号：US20140204956A1

    公开(公告)日：2014-07-24

    申请号：US14223507

    申请日：2014-03-24

    Applicant: Micron Technology, Inc.

    Inventor： David R. Brown ,  Harold B. Noyes ,  Irene Junjuan Xu ,  Paul Glendenning

    IPC: G06K9/00 ,  H04L12/883

    CPC classification number: G06F13/1673 ,  G06F9/4498 ,  G06F13/124 ,  G06F13/4022 ,  G06F13/4282 ,  G06F17/30516 ,  G06K9/00496 ,  G06K9/00973 ,  G06K9/00979 ,  H04L49/9021

    Abstract: A device includes a routing buffer. The routing buffer includes a first port configured to receive a signal relating to an analysis of at least a portion of a data stream. The routing buffer also includes a second port configured to selectively provide the signal to a first routing line of a block of a state machine at a first time. The routing buffer further includes a third port configured to selectively provide the signal to a second routing line of the block of the state machine at the first time.

    Abstract translation: 设备包括路由缓冲区。 路由缓冲器包括被配置为接收与数据流的至少一部分的分析有关的信号的第一端口。 路由缓冲器还包括被配置为在第一时间将信号选择性地提供给状态机的块的第一路由线的第二端口。 路由缓冲器还包括被配置为在第一时间将信号选择性地提供给状态机的块的第二路由选择线的第三端口。

Patent Agency Ranking