- Patent Title: 3D interconnect structure comprising through-silicon vias combined with fine pitch backside metal redistribution lines fabricated using a dual damascene type approach
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Application No.: US14836828Application Date: 2015-08-26
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Publication No.: US09530740B2Publication Date: 2016-12-27
- Inventor: Kevin J. Lee , Mark T. Bohr , Andrew W. Yeoh , Christopher M. Pelto , Hiten Kothari , Seshu V. Sattiraju , Hang-Shing Ma
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Blakely, Sokoloff, Taylor & Zafman LLP
- Main IPC: H01L23/48
- IPC: H01L23/48 ; H01L23/538 ; H01L21/768 ; H01L23/00 ; H01L23/522 ; H01L23/29 ; H01L23/31 ; H01L23/528 ; H01L21/683
Abstract:
A 3D interconnect structure and method of manufacture are described in which a through-silicon vias (TSVs) and metal redistribution layers (RDLs) are formed using a dual damascene type process flow. A silicon nitride or silicon carbide passivation layer may be provided between the thinned device wafer back side and the RDLs to provide a hermetic barrier and etch stop layer during the process flow.
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