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    Techniques for forming logic including integrated spin-transfer torque magnetoresistive random-access memory
    1.
    发明授权
    Techniques for forming logic including integrated spin-transfer torque magnetoresistive random-access memory 有权

    公开(公告)号：US10811595B2

    公开(公告)日：2020-10-20

    申请号：US16073687

    申请日：2016-04-01

    申请人： INTEL CORPORATION

    发明人： Kevin J. Lee ,  Oleg Golonzka ,  Tahir Ghani ,  Ruth A. Brain ,  Yih Wang

    IPC分类号： H01L43/02 ,  H01L27/22 ,  H01L43/12 ,  H01L43/08 ,  H01L43/10 ,  H01L43/14

    摘要： Techniques are disclosed for forming a logic device including integrated spin-transfer torque magnetoresistive random-access memory (STT-MRAM). In accordance with some embodiments, one or more magnetic tunnel junction (MTJ) devices may be formed within a given back-end-of-line (BEOL) interconnect layer of a host logic device. A given MTJ device may be formed, in accordance with some embodiments, over an electrically conductive layer configured to serve as a pedestal layer for the MTJ's constituent magnetic and insulator layers. In accordance with some embodiments, one or more conformal spacer layers may be formed over sidewalls of a given MTJ device and attendant pedestal layer, providing protection from oxidation and corrosion. A given MTJ device may be electrically coupled with an underlying interconnect or other electrically conductive feature, for example, by another intervening electrically conductive layer configured to serve as a thin via, in accordance with some embodiments.

    Logic Chip Including Embedded Magnetic Tunnel Junctions
    4.
    发明申请
    Logic Chip Including Embedded Magnetic Tunnel Junctions 审中-公开

    公开(公告)号：US20170358740A1

    公开(公告)日：2017-12-14

    申请号：US15596650

    申请日：2017-05-16

    申请人： Intel Corporation

    发明人： Kevin J. Lee ,  Tahir Ghani ,  Joseph M. Steigerwald ,  John H. Epple ,  Yih Wang

    IPC分类号： H01L43/12 ,  H01L27/22 ,  H01L43/08

    CPC分类号： H01L27/222 ,  G11C11/161 ,  H01L43/08 ,  H01L43/12

    摘要： An embodiment integrates memory, such as spin-torque transfer magnetoresistive random access memory (STT-MRAM) within a logic chip. The STT-MRAM includes a magnetic tunnel junction (MTJ) that has an upper MTJ layer, a lower MTJ layer, and a tunnel barrier directly contacting the upper MTJ layer and the lower MTJ layer; wherein the upper MTJ layer includes an upper MTJ layer sidewall and the lower MTJ layer includes a lower MTJ sidewall horizontally offset from the upper MTJ layer. Another embodiment includes a memory area, comprising a MTJ, and a logic area located on a substrate; wherein a horizontal plane intersects the MTJ, a first Inter-Layer Dielectric (ILD) material adjacent the MTJ, and a second ILD material included in the logic area, the first and second ILD materials being unequal to one another. Other embodiments are described herein.

    Logic chip including embedded magnetic tunnel junctions
    6.
    发明授权
    Logic chip including embedded magnetic tunnel junctions 有权
    逻辑芯片包括嵌入式磁隧道结

    公开(公告)号：US09041146B2

    公开(公告)日：2015-05-26

    申请号：US13994716

    申请日：2013-03-15

    申请人： Intel Corporation

    发明人： Kevin J. Lee ,  Tahir Ghani ,  Joseph M. Steigerwald ,  John H. Epple ,  Yih Wang

    IPC分类号： H01L43/02 ,  H01L43/12 ,  H01L43/08 ,  H01L27/22

    CPC分类号： H01L43/12 ,  G11C11/161 ,  H01L27/222 ,  H01L27/226 ,  H01L43/08

    摘要： An embodiment integrates memory, such as spin-torque transfer magnetoresistive random access memory (STT-MRAM) within a logic chip. The STT-MRAM includes a magnetic tunnel junction (MTJ) with an upper MTJ layer, lower MTJ layer, and tunnel barrier directly contacting the upper MTJ layer and the lower MTJ layer; wherein the upper MTJ layer includes an upper MTJ layer sidewall and the lower MTJ layer includes a lower MTJ sidewall horizontally offset from the upper MTJ layer. Another embodiment includes a memory area, comprising a MTJ, and a logic area located on a substrate; wherein a horizontal plane intersects the MTJ, a first Inter-Layer Dielectric (ILD) material adjacent the MTJ, and a second ILD material included in the logic area, the first and second ILD materials being unequal to one another. In an embodiment the first and second ILDs directly contact one another. Other embodiments are described herein.

    摘要翻译： 实施例将逻辑芯片内的诸如自旋转矩传递磁阻随机存取存储器（STT-MRAM）的存储器集成。 STT-MRAM包括具有上部MTJ层，较低MTJ层和直接接触上层MTJ层和下层MTJ层的隧道势垒的磁隧道结（MTJ）; 其中上MTJ层包括上MTJ层侧壁，下MTJ层包括水平地偏离上MTJ层的下MTJ侧壁。 另一个实施例包括包含MTJ的存储区域和位于衬底上的逻辑区域; 其中水平面与MTJ相邻，邻近MTJ的第一层间电介质（ILD）材料和包含在逻辑区域中的第二ILD材料，第一和第二ILD材料彼此不相等。 在一个实施例中，第一和第二ILD直接彼此接触。 本文描述了其它实施例。

    LANDING STRUCTURE FOR THROUGH-SILICON VIA
    7.
    发明申请
    LANDING STRUCTURE FOR THROUGH-SILICON VIA 审中-公开
    通过硅的接地结构

    公开(公告)号：US20150137368A1

    公开(公告)日：2015-05-21

    申请号：US14563926

    申请日：2014-12-08

    申请人： Intel Corporation

    发明人： Christopher M. Pelto ,  Ruth A. Brain ,  Kevin J. Lee ,  Gerald S. Leatherman

    IPC分类号： H01L23/48 ,  H01L21/768 ,  H01L23/522

    CPC分类号： H01L23/481 ,  H01L21/76879 ,  H01L21/76898 ,  H01L23/522 ,  H01L23/5226 ,  H01L2224/16225 ,  H01L2924/15311

    摘要： Embodiments of the present disclosure describe techniques and configurations associated with forming a landing structure for a through-silicon via (TSV) using interconnect structures of interconnect layers. In one embodiment, an apparatus includes a semiconductor substrate having a first surface and a second surface opposite to the first surface, a device layer disposed on the first surface of the semiconductor substrate, the device layer including one or more transistor devices, interconnect layers disposed on the device layer, the interconnect layers including a plurality of interconnect structures and one or more through-silicon vias disposed between the first surface and the second surface, wherein the plurality of interconnect structures include interconnect structures that are electrically coupled with the one or more TSVs and configured to provide one or more corresponding landing structures of the one or more TSVs. Other embodiments may be described and/or claimed.

    摘要翻译： 本公开的实施例描述与使用互连层的互连结构形成用于穿硅通孔（TSV）的着陆结构相关联的技术和配置。 在一个实施例中，一种装置包括具有第一表面和与第一表面相对的第二表面的半导体衬底，设置在半导体衬底的第一表面上的器件层，器件层包括一个或多个晶体管器件，布置的互连层 在所述器件层上，所述互连层包括多个互连结构以及设置在所述第一表面和所述第二表面之间的一个或多个穿硅通孔，其中所述多个互连结构包括互连结构，所述互连结构与所述一个或多个 TSV并且被配置为提供一个或多个TSV的一个或多个相应的着陆结构。 可以描述和/或要求保护其他实施例。

    Logic chip including embedded magnetic tunnel junctions
    9.
    发明授权
    Logic chip including embedded magnetic tunnel junctions 有权

    公开(公告)号：US09997563B2

    公开(公告)日：2018-06-12

    申请号：US15596650

    申请日：2017-05-16

    申请人： Intel Corporation

    发明人： Kevin J. Lee ,  Tahir Ghani ,  Joseph M. Steigerwald ,  John H. Epple ,  Yih Wang

    IPC分类号： H01L27/22 ,  H01L43/12 ,  H01L43/08

    CPC分类号： H01L27/222 ,  G11C11/161 ,  H01L43/08 ,  H01L43/12

    摘要： An embodiment integrates memory, such as spin-torque transfer magnetoresistive random access memory (STT-MRAM) within a logic chip. The STT-MRAM includes a magnetic tunnel junction (MTJ) that has an upper MTJ layer, a lower MTJ layer, and a tunnel barrier directly contacting the upper MTJ layer and the lower MTJ layer; wherein the upper MTJ layer includes an upper MTJ layer sidewall and the lower MTJ layer includes a lower MTJ sidewall horizontally offset from the upper MTJ layer. Another embodiment includes a memory area, comprising a MTJ, and a logic area located on a substrate; wherein a horizontal plane intersects the MTJ, a first Inter-Layer Dielectric (ILD) material adjacent the MTJ, and a second ILD material included in the logic area, the first and second ILD materials being unequal to one another. Other embodiments are described herein.