公开(公告)号：US20240063120A1

公开(公告)日：2024-02-22

申请号：US17820961

申请日：2022-08-19

Applicant: Intel Corporation

Inventor： Adel A. Elsherbini ,  Shawna M. Liff ,  Debendra Mallik ,  Christopher M. Pelto ,  Kimin Jun ,  Johanna M. Swan ,  Lei Jiang ,  Feras Eid ,  Krishna Vasanth Valavala ,  Henning Braunisch ,  Patrick Morrow ,  William J. Lambert

IPC: H01L23/528 ,  H01L23/00 ,  H01L25/065 ,  H01L23/48 ,  H01L23/498 ,  H01L23/522 ,  H01L21/48

CPC classification number: H01L23/5286 ,  H01L24/08 ,  H01L24/05 ,  H01L24/16 ,  H01L25/0652 ,  H01L23/481 ,  H01L23/49811 ,  H01L23/49822 ,  H01L23/49833 ,  H01L23/49838 ,  H01L23/5283 ,  H01L23/5226 ,  H01L24/80 ,  H01L21/4853 ,  H01L21/4857 ,  H01L2924/37001 ,  H01L2924/3841 ,  H01L2924/3512 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2224/05647 ,  H01L2224/05687 ,  H01L2224/08121 ,  H01L2224/08145 ,  H01L2224/08225 ,  H01L2224/16225

Abstract: Embodiments of a microelectronic assembly comprise: a plurality of layers of integrated circuit (IC) dies, each layer coupled to adjacent layers by first interconnects having a pitch of less than 10 micrometers between adjacent first interconnects; an end layer in the plurality of layers proximate to a first side of the plurality of layers comprises a dielectric material around IC dies in the end layer and a through-dielectric via (TDV) in the dielectric material of the end layer; a support structure coupled to the first side of the plurality of layers, the support structure comprising a structurally stiff base with conductive traces proximate to the end layer, the conductive traces coupled to the end layer by second interconnects; and a package substrate coupled to a second side of the plurality of layers, the second side being opposite to the first side.

公开(公告)号：US11222863B2

公开(公告)日：2022-01-11

申请号：US16080989

申请日：2016-04-01

Applicant: Intel Corporation

Inventor： Fay Hua ,  Christopher M. Pelto ,  Valluri R. Rao ,  Mark T. Bohr ,  Johanna M. Swan

IPC: H01L23/00 ,  H01L21/02 ,  H01L21/768 ,  H01L21/78 ,  H01L25/065 ,  H01L25/00

Abstract: Embodiments of the present disclosure describe techniques for fabricating a stacked integrated circuit (IC) device. A first wafer that includes a plurality of first IC dies may be sorted to identify first known good dies of the plurality of first IC dies. The first wafer may be diced to singulate the first IC dies. A second wafer that includes a plurality of second IC dies may be sorted to identify second know good dies of the plurality of second IC dies. The first known good dies may be bonded to respective second known good dies of the second wafer. In some embodiments, the first known good dies may be thinned after bonding the first know good dies to the second wafer. Other embodiments may be described and/or claimed.

公开(公告)号：US20230369503A1

公开(公告)日：2023-11-16

申请号：US17742664

申请日：2022-05-12

Applicant: Intel Corporation

Inventor： Cheng Tan ,  Van H. Le ,  Akash Garg ,  Shokir A. Pardaev ,  Timothy Jen ,  Abhishek Anil Sharma ,  Thiruselvam Ponnusamy ,  Moira C. Vyner ,  Caleb Barrett ,  Forough Mahmoudabadi ,  Albert B. Chen ,  Travis W. Lajoie ,  Christopher M. Pelto

IPC: H01L29/786 ,  H01L23/522 ,  H01L27/108 ,  H01L29/417

CPC classification number: H01L29/78618 ,  H01L23/5226 ,  H01L27/10805 ,  H01L29/7869 ,  H01L29/41733

Abstract: Techniques are provided for making asymmetric contacts to improve the performance of thin film transistors (TFT) structures. The asymmetry may be with respect to the area of contact interface with the semiconductor region and/or the depth to which the contacts extend into the semiconductor region. According to some embodiments, the TFT structures are used in memory structures arranged in a two-dimensional array within one or more interconnect layers and stacked in a vertical direction such that multiple tiers of memory structure arrays are formed within the interconnect region. Any of the given TFT structures may include asymmetric contacts, such as two contacts that each have a different contact area to a semiconductor region, and/or that extend to different depths within the semiconductor region. The degree of asymmetry may be tuned during fabrication to modulate certain transistor parameters such as, for example, leakage, capacitance, gate control, channel length, or contact resistance.

公开(公告)号：US20170011997A1

公开(公告)日：2017-01-12

申请号：US15274175

申请日：2016-09-23

Applicant: Intel Corporation

Inventor： Kevin J. Fischer ,  Christopher M. Pelto ,  Andrew W. Yeoh

IPC: H01L23/528 ,  H01L23/532 ,  H01L21/768 ,  H01L23/522

CPC classification number: H01L23/5283 ,  H01L21/76852 ,  H01L21/76879 ,  H01L21/76885 ,  H01L23/522 ,  H01L23/5226 ,  H01L23/5286 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An embodiment includes a semiconductor structure comprising: a frontend portion including a device layer; a backend portion including a bottom metal layer, a top metal layer, and intermediate metal layers between the bottom and top metal layers; wherein (a) the top metal layer includes a first thickness that is orthogonal to the horizontal plane in which the top metal layer lies, the bottom metal layer includes a second thickness; and the intermediate metal layers includes a third thickness; and (b) the first thickness is greater than or equal to a sum of the second and third thicknesses. Other embodiments are described herein.

Abstract translation: 实施例包括半导体结构，包括：包括器件层的前端部分; 后底部分，其包括底部金属层，顶部金属层和位于底部和顶部金属层之间的中间金属层; 其中（a）顶部金属层包括与顶部金属层所在的水平面正交的第一厚度，底部金属层包括第二厚度; 并且所述中间金属层包括第三厚度; 和（b）第一厚度大于或等于第二和第三厚度之和。 本文描述了其它实施例。

公开(公告)号：US09496173B2

公开(公告)日：2016-11-15

申请号：US14137487

申请日：2013-12-20

Applicant: Intel Corporation

Inventor： Kevin J. Fischer ,  Christopher M. Pelto ,  Andrew W. Yeoh

IPC: H01L23/498 ,  H01L23/522 ,  H01L21/68 ,  H01L21/768 ,  H01L23/528 ,  H01L23/532

CPC classification number: H01L23/5283 ,  H01L21/76852 ,  H01L21/76879 ,  H01L21/76885 ,  H01L23/522 ,  H01L23/5226 ,  H01L23/5286 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An embodiment includes a semiconductor structure comprising: a frontend portion including a device layer; a backend portion including a bottom metal layer, a top metal layer, and intermediate metal layers between the bottom and top metal layers; wherein (a) the top metal layer includes a first thickness that is orthogonal to the horizontal plane in which the top metal layer lies, the bottom metal layer includes a second thickness; and the intermediate metal layers includes a third thickness; and (b) the first thickness is greater than or equal to a sum of the second and third thicknesses. Other embodiments are described herein.

Abstract translation: 实施例包括半导体结构，包括：包括器件层的前端部分; 后底部分，其包括底部金属层，顶部金属层和位于底部和顶部金属层之间的中间金属层; 其中（a）顶部金属层包括与顶部金属层所在的水平面正交的第一厚度，底部金属层包括第二厚度; 并且所述中间金属层包括第三厚度; 和（b）第一厚度大于或等于第二和第三厚度之和。 本文描述了其它实施例。

公开(公告)号：US12107040B2

公开(公告)日：2024-10-01

申请号：US17129858

申请日：2020-12-21

Applicant: Intel Corporation

Inventor： Aaron J. Welsh ,  Christopher M. Pelto ,  David J. Towner ,  Mark A. Blount ,  Takayoshi Ito ,  Dragos Seghete ,  Christopher R. Ryder ,  Stephanie F. Sundholm ,  Chamara Abeysekera ,  Anil W. Dey ,  Che-Yun Lin ,  Uygar E. Avci

IPC: H01L23/522 ,  H01L27/08 ,  H01L49/02

CPC classification number: H01L23/5223 ,  H01L28/60

Abstract: Metal insulator metal capacitors are described. In an example, a capacitor includes a first electrode plate, and a first capacitor dielectric on the first electrode plate. A second electrode plate is on the first capacitor dielectric and is over and parallel with the first electrode plate, and a second capacitor dielectric is on the second electrode plate. A third electrode plate is on the second capacitor dielectric and is over and parallel with the second electrode plate, and a third capacitor dielectric is on the third electrode plate. A fourth electrode plate is on the third capacitor dielectric and is over and parallel with the third electrode plate. In another example, a capacitor includes a first electrode, a capacitor dielectric on the first electrode, and a second electrode on the capacitor dielectric. The capacitor dielectric includes a plurality of alternating first dielectric layers and second dielectric layers.

公开(公告)号：US20230187362A1

公开(公告)日：2023-06-15

申请号：US17548078

申请日：2021-12-10

Applicant: Intel Corporation

Inventor： Adel A. Elsherbini ,  Christopher M. Pelto ,  Kimin Jun ,  Brandon M. Rawlings ,  Shawna M. Liff ,  Bradley A. Jackson ,  Robert J. Munoz ,  Johanna M. Swan

IPC: H01L23/538 ,  H01L25/065 ,  H01L23/498 ,  H01L25/00 ,  H01L23/00

CPC classification number: H01L23/5383 ,  H01L25/0652 ,  H01L23/49894 ,  H01L25/50 ,  H01L24/96

Abstract: A microelectronic assembly is provided, comprising: a first plurality of integrated circuit (IC) dies in a first layer; a second plurality of IC dies in a second layer; and a third plurality of IC dies in a third layer, in which: the second layer is between the first layer and the third layer, an interface between two adjacent layers comprises interconnects having a pitch of less than 10 micrometers between adjacent ones of the interconnects, and each of the first layer, the second layer, and the third layer comprises a dielectric material, and further comprises conductive traces in the dielectric material.

公开(公告)号：US20230170327A1

公开(公告)日：2023-06-01

申请号：US17538603

申请日：2021-11-30

Applicant: Intel Corporation

Inventor： Jin Yang ,  David Shia ,  Adel A. Elsherbini ,  Christopher M. Pelto ,  Kimin Jun ,  Bradley A. Jackson ,  Robert J. Munoz ,  Shawna M. Liff ,  Johanna M. Swan

IPC: H01L25/065 ,  H01L25/00

CPC classification number: H01L25/0657 ,  H01L25/50 ,  H01L25/0652 ,  H01L2225/06517 ,  H01L24/08

Abstract: A microelectronic assembly is provided, comprising: a first IC die coupled to a surface with first interconnects having a first pitch; and a second IC die coupled to the surface with second interconnects having a second pitch. The second pitch is greater than the first pitch, and the first pitch is less than 10 micrometers. In another embodiment, a microelectronic assembly is provided, comprising: a first stack coupled to a surface, the first stack comprising a first number of IC dies; and a second stack coupled to the surface, the second stack comprising a second number of IC dies, in which: the first stack and the second stack are laterally surrounded by a dielectric, the first stack and the second stack have a same thickness, and the first number is less than the second number.

公开(公告)号：US10229879B2

公开(公告)日：2019-03-12

申请号：US15274175

申请日：2016-09-23

Applicant: Intel Corporation

Inventor： Kevin J. Fischer ,  Christopher M. Pelto ,  Andrew W. Yeoh

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/532 ,  H01L23/528

Abstract: An embodiment includes a semiconductor structure comprising: a frontend portion including a device layer; a backend portion including a bottom metal layer, a top metal layer, and intermediate metal layers between the bottom and top metal layers; wherein (a) the top metal layer includes a first thickness that is orthogonal to the horizontal plane in which the top metal layer lies, the bottom metal layer includes a second thickness; and the intermediate metal layers includes a third thickness; and (b) the first thickness is greater than or equal to a sum of the second and third thicknesses. Other embodiments are described herein.

公开(公告)号：US20150137368A1

公开(公告)日：2015-05-21

申请号：US14563926

申请日：2014-12-08

Applicant: Intel Corporation

Inventor： Christopher M. Pelto ,  Ruth A. Brain ,  Kevin J. Lee ,  Gerald S. Leatherman

IPC: H01L23/48 ,  H01L21/768 ,  H01L23/522

CPC classification number: H01L23/481 ,  H01L21/76879 ,  H01L21/76898 ,  H01L23/522 ,  H01L23/5226 ,  H01L2224/16225 ,  H01L2924/15311

Abstract: Embodiments of the present disclosure describe techniques and configurations associated with forming a landing structure for a through-silicon via (TSV) using interconnect structures of interconnect layers. In one embodiment, an apparatus includes a semiconductor substrate having a first surface and a second surface opposite to the first surface, a device layer disposed on the first surface of the semiconductor substrate, the device layer including one or more transistor devices, interconnect layers disposed on the device layer, the interconnect layers including a plurality of interconnect structures and one or more through-silicon vias disposed between the first surface and the second surface, wherein the plurality of interconnect structures include interconnect structures that are electrically coupled with the one or more TSVs and configured to provide one or more corresponding landing structures of the one or more TSVs. Other embodiments may be described and/or claimed.

Abstract translation: 本公开的实施例描述与使用互连层的互连结构形成用于穿硅通孔（TSV）的着陆结构相关联的技术和配置。 在一个实施例中，一种装置包括具有第一表面和与第一表面相对的第二表面的半导体衬底，设置在半导体衬底的第一表面上的器件层，器件层包括一个或多个晶体管器件，布置的互连层 在所述器件层上，所述互连层包括多个互连结构以及设置在所述第一表面和所述第二表面之间的一个或多个穿硅通孔，其中所述多个互连结构包括互连结构，所述互连结构与所述一个或多个 TSV并且被配置为提供一个或多个TSV的一个或多个相应的着陆结构。 可以描述和/或要求保护其他实施例。