Provided is a memory device including a stack structure, a plurality of first cap layers, and a plurality of second cap layers. The stack structure is located on a substrate. The stack structure includes a plurality of first conductive layers and a plurality of dielectric layers. The first conductive layers and the dielectric layers are stacked alternately. The first cap layers are located on sidewalls of the first conductive layers respectively. The second cap layers are located on sidewalls of the dielectric layers respectively.