Invention Grant
US09536611B2 3D NAND memory using two separate SSL structures in an interlaced configuration for one bit line 有权
3D NAND存储器使用两个独立的SSL结构,以隔行扫描配置一条位线

3D NAND memory using two separate SSL structures in an interlaced configuration for one bit line
Abstract:
A semiconductor device includes a plurality of active strips, where active strips in the plurality are coupled together at one end by a pad and terminated at another end by a conductive line. The device includes memory cells at cross-points between the plurality of active strips and a plurality of word lines. The device includes string select structures arranged in an interlaced configuration as side gates for active strips. The device includes control circuitry, configured to turn on a particular active strip by applying a turn-on voltage to two string select structures arranged as side gates for the particular active strip, and to turn off a second particular active strip by applying a turn-off bias to at least one string select structure arranged as a side gate for the second particular active strip. The turn-off bias includes one of a ground voltage, a non-negative voltage, and a floating condition.
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