公开(公告)号：US09425191B2

公开(公告)日：2016-08-23

申请号：US13965269

申请日：2013-08-13

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Yi-Hsuan Hsiao ,  Yen-Hao Shih ,  Shih-Hung Chen ,  Hang-Ting Lue

IPC: H01L27/06 ,  H01L27/115

CPC classification number: H01L27/0688 ,  H01L27/11531 ,  H01L27/11551 ,  H01L27/11573 ,  H01L27/11578

Abstract: A memory device and a manufacturing method of the same are provided. The memory device includes a substrate, a 3D memory array, a periphery circuit, and a conductive connection structure. The 3D memory array and the periphery circuit are stacked on the substrate. The periphery circuit includes a patterned metal layer and a contact structure electrically connected to the patterned metal layer. The conductive connection structure is electrically connected to the patterned metal layer. The 3D memory array is electrically connected to the periphery circuit via the conductive connection structure.

Abstract translation: 提供了一种存储器件及其制造方法。 存储器件包括衬底，3D存储器阵列，外围电路和导电连接结构。 3D存储器阵列和外围电路堆叠在基板上。 外围电路包括图案化金属层和电连接到图案化金属层的接触结构。 导电连接结构电连接到图案化的金属层。 3D存储器阵列经由导电连接结构电连接到外围电路。

公开(公告)号：US09536611B2

公开(公告)日：2017-01-03

申请号：US13887019

申请日：2013-05-03

Applicant: Macronix International Co., Ltd.

Inventor： Yen-Hao Shih ,  Yi-Hsuan Hsiao

IPC: G11C16/10 ,  H01L27/115

CPC classification number: G11C16/10 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11582

Abstract: A semiconductor device includes a plurality of active strips, where active strips in the plurality are coupled together at one end by a pad and terminated at another end by a conductive line. The device includes memory cells at cross-points between the plurality of active strips and a plurality of word lines. The device includes string select structures arranged in an interlaced configuration as side gates for active strips. The device includes control circuitry, configured to turn on a particular active strip by applying a turn-on voltage to two string select structures arranged as side gates for the particular active strip, and to turn off a second particular active strip by applying a turn-off bias to at least one string select structure arranged as a side gate for the second particular active strip. The turn-off bias includes one of a ground voltage, a non-negative voltage, and a floating condition.

Abstract translation: 半导体器件包括多个有源条，其中多个有源条在一端通过焊盘耦合在一起，并在另一端由导线连接。 该装置包括位于多个活动条和多个字线之间的交叉点处的存储单元。 该装置包括以隔行扫描配置布置的串选择结构，作为活动条的侧门。 该装置包括控制电路，其被配置为通过向作为特定有源条的侧栅排列的两个串选择结构施加导通电压来接通特定有源条，并且通过施加转向电压来关闭第二特定有源条， 对至少一个排列为第二特定有源条的侧栅极的串选择结构的偏置偏压。 关断偏压包括接地电压，非负电压和浮置状态之一。

公开(公告)号：US20160141300A1

公开(公告)日：2016-05-19

申请号：US14541169

申请日：2014-11-14

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Yi-Hsuan Hsiao ,  Wei-Chen Chen

IPC: H01L27/115

CPC classification number: H01L27/11582 ,  H01L27/11575

Abstract: A three-dimensional (3D) memory and a method for manufacturing the same are disclosed. According to one embodiment, the 3D memory comprises a thin-film transistor. The thin-film transistor has a source region and a drain region disposed separately. The source region comprises a first source region and a second source region disposed between the first source region and the drain region. The first source region is p-type of doping, the second source region is n-type of doping, and the drain region is n-type of doping.

Abstract translation: 公开了一种三维（3D）存储器及其制造方法。 根据一个实施例，3D存储器包括薄膜晶体管。 薄膜晶体管具有单独设置的源极区域和漏极区域。 源极区域包括设置在第一源极区域和漏极区域之间的第一源极区域和第二源极区域。 第一源区是p型掺杂，第二源区是n型掺杂，漏区是n型掺杂。

公开(公告)号：US20150048506A1

公开(公告)日：2015-02-19

申请号：US13965269

申请日：2013-08-13

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Yi-Hsuan Hsiao ,  Yen-Hao Shih ,  Shih-Hung Chen ,  Hang-Ting Lue

IPC: H01L27/06 ,  H01L27/105 ,  H01L27/12

CPC classification number: H01L27/0688 ,  H01L27/11531 ,  H01L27/11551 ,  H01L27/11573 ,  H01L27/11578

Abstract: A memory device and a manufacturing method of the same are provided. The memory device includes a substrate, a 3D memory array, a periphery circuit, and a conductive connection structure. The 3D memory array and the periphery circuit are stacked on the substrate. The periphery circuit includes a patterned metal layer and a contact structure electrically connected to the patterned metal layer. The conductive connection structure is electrically connected to the patterned metal layer. The 3D memory array is electrically connected to the periphery circuit via the conductive connection structure.

Abstract translation: 提供了一种存储器件及其制造方法。 存储器件包括衬底，3D存储器阵列，外围电路和导电连接结构。 3D存储器阵列和外围电路堆叠在基板上。 外围电路包括图案化金属层和电连接到图案化金属层的接触结构。 导电连接结构电连接到图案化的金属层。 3D存储器阵列经由导电连接结构电连接到外围电路。

公开(公告)号：US20140035140A1

公开(公告)日：2014-02-06

申请号：US14049253

申请日：2013-10-09

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Hang-Ting Lue ,  Yi-Hsuan Hsiao

IPC: H01L23/485 ,  H01L23/00

CPC classification number: H01L23/485 ,  H01L24/64 ,  H01L27/11578 ,  H01L29/4234 ,  H01L29/792

Abstract: A semiconductor structure and a method for manufacturing the same are provided. The method comprises following steps. A first silicon-containing conductive material is formed on a substrate. A second silicon-containing conductive material is formed on the first silicon-containing conductive material. The first silicon-containing conductive material and the second silicon-containing conductive material have different dopant conditions. The first silicon-containing conductive material and the second silicon-containing conductive material are thermally oxidized for turning the first silicon-containing conductive material wholly into an insulating oxide structure, and the second silicon-containing conductive material into a silicon-containing conductive structure and an insulating oxide layer.

Abstract translation: 提供半导体结构及其制造方法。 该方法包括以下步骤。 在基板上形成第一含硅导电材料。 在第一含硅导电材料上形成第二含硅导电材料。 第一含硅导电材料和第二含硅导电材料具有不同的掺杂条件。 第一含硅导电材料和第二含硅导电材料被热氧化，以将第一含硅导电材料完全转变成绝缘氧化物结构，第二含硅导电材料变成含硅导电结构， 绝缘氧化物层。

公开(公告)号：US09214351B2

公开(公告)日：2015-12-15

申请号：US13970482

申请日：2013-08-19

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Yi-Hsuan Hsiao ,  Hang-Ting Lue ,  Wei-Chen Chen

IPC: G11C16/04 ,  H01L21/28 ,  H01L29/792 ,  H01L27/115 ,  G11C16/34 ,  G11C16/10 ,  G11C16/26

CPC classification number: G11C16/0483 ,  G11C16/10 ,  G11C16/26 ,  G11C16/3418 ,  H01L21/28282 ,  H01L27/11578 ,  H01L29/7926

Abstract: A 3D memory device includes an improved dual gate memory cell. The improved dual gate memory cell has a channel body with opposing first and second side surfaces, charge storage structures on the first and second side surfaces, and a gate structure overlying the charge storage structures on both the first and second side surfaces. The channel body has a depth between the first and second side surfaces less than a threshold channel body depth, combined with the gate structure which establishes an effective channel length of the cell greater than a threshold length. The combination of the channel body depth and effective channel length are related so that the cell channel body can be fully depleted, and sub-threshold leakage current can be suppressed when the memory cell has a high threshold state under a read bias.

Abstract translation: 3D存储器件包括改进的双栅极存储单元。 改进的双栅极存储单元具有通道体，其具有相对的第一和第二侧表面，第一和第二侧表面上的电荷存储结构以及覆盖第一和第二侧表面上的电荷存储结构的栅极结构。 通道体具有小于阈值通道体深度的第一和第二侧表面之间的深度，与构成该单元的有效通道长度大于阈值长度的栅极结构组合。 通道体深度与有效沟道长度的组合是相关联的，使得单元通道体可以完全耗尽，并且当存储单元在读取偏压下具有高阈值状态时，可以抑制亚阈值泄漏电流。

公开(公告)号：US09087825B2

公开(公告)日：2015-07-21

申请号：US14049253

申请日：2013-10-09

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Hang-Ting Lue ,  Yi-Hsuan Hsiao

IPC: H01L23/485 ,  H01L27/115 ,  H01L29/423 ,  H01L29/792 ,  H01L23/00

CPC classification number: H01L23/485 ,  H01L24/64 ,  H01L27/11578 ,  H01L29/4234 ,  H01L29/792

Abstract: A semiconductor structure and a method for manufacturing the same are provided. The method comprises following steps. A first silicon-containing conductive material is formed on a substrate. A second silicon-containing conductive material is formed on the first silicon-containing conductive material. The first silicon-containing conductive material and the second silicon-containing conductive material have different dopant conditions. The first silicon-containing conductive material and the second silicon-containing conductive material are thermally oxidized for turning the first silicon-containing conductive material wholly into an insulating oxide structure, and the second silicon-containing conductive material into a silicon-containing conductive structure and an insulating oxide layer.

Abstract translation: 提供半导体结构及其制造方法。 该方法包括以下步骤。 在基板上形成第一含硅导电材料。 在第一含硅导电材料上形成第二含硅导电材料。 第一含硅导电材料和第二含硅导电材料具有不同的掺杂条件。 第一含硅导电材料和第二含硅导电材料被热氧化，以将第一含硅导电材料完全转变成绝缘氧化物结构，第二含硅导电材料变成含硅导电结构， 绝缘氧化物层。

公开(公告)号：US09536893B2

公开(公告)日：2017-01-03

申请号：US14541169

申请日：2014-11-14

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Yi-Hsuan Hsiao ,  Wei-Chen Chen

IPC: H01L21/283 ,  H01L23/48 ,  H01L23/535 ,  H01L21/768 ,  H01L23/528 ,  H01L27/115

CPC classification number: H01L27/11582 ,  H01L27/11575

Abstract: A three-dimensional (3D) memory and a method for manufacturing the same are disclosed. According to one embodiment, the 3D memory comprises a thin-film transistor. The thin-film transistor has a source region and a drain region disposed separately. The source region comprises a first source region and a second source region disposed between the first source region and the drain region. The first source region is p-type of doping, the second source region is n-type of doping, and the drain region is n-type of doping.

Abstract translation: 公开了一种三维（3D）存储器及其制造方法。 根据一个实施例，3D存储器包括薄膜晶体管。 薄膜晶体管具有单独设置的源极区域和漏极区域。 源极区域包括设置在第一源极区域和漏极区域之间的第一源极区域和第二源极区域。 第一源区是p型掺杂，第二源区是n型掺杂，漏区是n型掺杂。

公开(公告)号：US09252156B2

公开(公告)日：2016-02-02

申请号：US14633040

申请日：2015-02-26

Applicant: Macronix International Co., Ltd.

Inventor： Yen-Hao Shih ,  Yi-Hsuan Hsiao ,  Chih-Ping Chen

IPC: H01L27/115

CPC classification number: H01L27/11582 ,  H01L27/11551 ,  H01L27/11573 ,  H01L27/11575

Abstract: A method of forming an interlayer conductor structure. The method includes forming a stack of semiconductor pads coupled to respective active layers for a circuit. The semiconductor pads include outside perimeters each having one side coupled to a respective active layer. Impurities are implanted along the outside perimeters to form outside lower resistance regions on the pads. Openings are then formed in the stack of the semiconductor pads to expose a landing area for interlayer conductors on a corresponding semiconductor pad and to define an inside perimeter on at least one of the semiconductor pads. Inside lower resistance regions are formed along the inside perimeters by implanting impurities for interlayer conductor contacts and configured to overlap and be continuous with the corresponding outside lower resistance region.

公开(公告)号：US08987914B2

公开(公告)日：2015-03-24

申请号：US13907607

申请日：2013-05-31

Applicant: Macronix International Co., Ltd.

Inventor： Yen-Hao Shih ,  Yi-Hsuan Hsiao ,  Chih-Ping Chen

IPC: H01L23/498 ,  H01L21/768 ,  H01L27/115

CPC classification number: H01L27/11582 ,  H01L27/11551 ,  H01L27/11573 ,  H01L27/11575

Abstract: A method of forming an interlayer conductor structure. The method includes forming a stack of semiconductor pads coupled to respective active layers for a circuit. The semiconductor pads include outside perimeters each having one side coupled to a respective active layer. Impurities are implanted along the outside perimeters to form outside lower resistance regions on the pads. Openings are then formed in the stack of the semiconductor pads to expose a landing area for interlayer conductors on a corresponding semiconductor pad and to define an inside perimeter on at least one of the semiconductor pads. Inside lower resistance regions are formed along the inside perimeters by implanting impurities for interlayer conductor contacts and configured to overlap and be continuous with the corresponding outside lower resistance region.

Abstract translation: 一种形成层间导体结构的方法。 该方法包括形成耦合到用于电路的相应有源层的半导体焊盘堆叠。 半导体焊盘包括外周边，每个外围具有耦合到相应有源层的一侧。 杂质沿着外部周边植入，以形成垫上的较低电阻区域外部。 然后在半导体焊盘的堆叠中形成开口，以暴露对应的半导体焊盘上的层间导体的着陆区域，并且在至少一个半导体焊盘上限定内部周边。 通过注入用于层间导体接触的杂质并且被配置为与相应的外部较低电阻区域重叠并连续地沿着内周边形成内部较低电阻区域。