Invention Grant
- Patent Title: Warpage control in the packaging of integrated circuits
- Patent Title (中): 集成电路封装中的翘曲控制
-
Application No.: US13559318Application Date: 2012-07-26
-
Publication No.: US09538582B2Publication Date: 2017-01-03
- Inventor: Ming-Da Cheng , Hsiu-Jen Lin , Cheng-Ting Chen , Wei-Yu Chen , Chien-Wei Lee , Chung-Shi Liu
- Applicant: Ming-Da Cheng , Hsiu-Jen Lin , Cheng-Ting Chen , Wei-Yu Chen , Chien-Wei Lee , Chung-Shi Liu
- Applicant Address: TW Hsin-Chu
- Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee Address: TW Hsin-Chu
- Agency: Slater Matsil, LLP
- Main IPC: B23K31/02
- IPC: B23K31/02 ; H01L21/00 ; H05B3/02 ; H01L21/677 ; H01L21/683 ; H01L23/00
Abstract:
A method includes placing a first package component over a vacuum boat, wherein the vacuum boat comprises a hole, and wherein the first package component covers the hole. A second package component is placed over the first package component, wherein solder regions are disposed between the first and the second package components. The hole is vacuumed, wherein the first package component is pressed by a pressure against the vacuum boat, and wherein the pressure is generated by a vacuum in the hole. When the vacuum in the hole is maintained, the solder regions are reflowed to bond the second package component to the first package component.
Public/Granted literature
- US20140027431A1 Warpage Control in the Packaging of Integrated Circuits Public/Granted day:2014-01-30
Information query
IPC分类:
