Invention Grant
US09543019B2 Error corrected pre-read for upper page write in a multi-level cell memory
有权
在多级单元存储器中对上页写入错误校正预读
- Patent Title: Error corrected pre-read for upper page write in a multi-level cell memory
- Patent Title (中): 在多级单元存储器中对上页写入错误校正预读
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Application No.: US13710913Application Date: 2012-12-11
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Publication No.: US09543019B2Publication Date: 2017-01-10
- Inventor: Robert E. Frickey , Yogesh B. Wakchaure , Iwen Chao , Xin Guo , Kristopher H. Gaewsky
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Alpine Technology Law Group LLC
- Main IPC: G06F11/10
- IPC: G06F11/10 ; G11C16/10 ; G11C11/56
Abstract:
Methods, apparatuses and articles of manufacture may receive a first page of data and correct one or more errors in the first page of data to generate a page of corrected data. A program command may then be sent with a second page of data and the page of corrected data, to program a page of memory to store the second page of data.
Public/Granted literature
- US20140164872A1 ERROR CORRECTED PRE-READ FOR UPPER PAGE WRITE IN A MULTI-LEVEL CELL MEMORY Public/Granted day:2014-06-12
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