Invention Grant
US09552849B2 Memory device with timing overlap mode and precharge timing circuit
有权
具有定时重叠模式和预充电定时电路的存储器件
- Patent Title: Memory device with timing overlap mode and precharge timing circuit
- Patent Title (中): 具有定时重叠模式和预充电定时电路的存储器件
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Application No.: US14973884Application Date: 2015-12-18
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Publication No.: US09552849B2Publication Date: 2017-01-24
- Inventor: Thomas Andre , Syed M. Alam , Halbert S Lin
- Applicant: Everspin Technologies, Inc.
- Applicant Address: US AZ Chandler
- Assignee: Everspin Technologies, Inc.
- Current Assignee: Everspin Technologies, Inc.
- Current Assignee Address: US AZ Chandler
- Main IPC: G11C7/00
- IPC: G11C7/00 ; G11C11/16 ; G11C7/10 ; G11C7/22 ; G11C11/4076
Abstract:
In some examples, a memory device is configured to receive a precharge command and an activate command. The memory device performs a first series of events related to the precharge command in response to receiving the precharge command and a second series of events related to the activate command in response to receiving the activate command. The memory device delays the start of the second series of events until the first series of events completes.
Public/Granted literature
- US20160104518A1 Memory Device With Timing Overlap Mode Public/Granted day:2016-04-14
Information query
