公开(公告)号：US12020770B2

公开(公告)日：2024-06-25

申请号：US18189738

申请日：2023-03-24

Applicant: Everspin Technologies, Inc.

Inventor： Syed M. Alam

IPC: G11C7/10 ,  G11C5/14

CPC classification number: G11C7/1069 ,  G11C5/146 ,  G11C7/1045 ,  G11C7/1096

Abstract: 1. The present disclosure is drawn to, among other things, a method for accessing memory using dual standby modes, the method including receiving a first standby mode indication selecting a first standby mode from a first standby mode or a second standby mode, configuring a read bias system to provide a read bias voltage and a write bias system to provide approximately no voltage, or any voltage outside the necessary range for write operation, based on the first standby mode, receiving a second standby mode indication selecting the second standby mode, and configuring the read bias system to provide at least the read bias voltage and the write bias system to provide a write bias voltage based on the second standby mode, the read bias voltage being lower than the write bias voltage.

公开(公告)号：US11651802B1

公开(公告)日：2023-05-16

申请号：US17455292

申请日：2021-11-17

Applicant: Everspin Technologies, Inc.

Inventor： Syed M. Alam

IPC: G11C7/10 ,  G11C5/14

CPC classification number: G11C7/1069 ,  G11C5/146 ,  G11C7/1045 ,  G11C7/1096

Abstract: The present disclosure is drawn to, among other things, a method for accessing memory using dual standby modes, the method including receiving a first standby mode indication selecting a first standby mode from a first standby mode or a second standby mode, configuring a read bias system to provide a read bias voltage and a write bias system to provide approximately no voltage, or any voltage outside the necessary range for write operation, based on the first standby mode, receiving a second standby mode indication selecting the second standby mode, and configuring the read bias system to provide at least the read bias voltage and the write bias system to provide a write bias voltage based on the second standby mode, the read bias voltage being lower than the write bias voltage.

公开(公告)号：US11176974B2

公开(公告)日：2021-11-16

申请号：US16518146

申请日：2019-07-22

Applicant: Everspin Technologies, Inc.

Inventor： Syed M. Alam ,  Thomas S. Andre

IPC: G11C7/12 ,  G11C7/06 ,  G11C5/06

Abstract: In some examples, a memory device may have at least a first and a second memory array. In some cases, a portion of the bit cells of the first memory array may be coupled to first PMOS-follower circuitry and to second PMOS-follower circuitry. A portions of the bit cells of the second memory array may also be coupled to the second PMOS-follower circuitry and to third PMOS-follower circuitry. Additionally, in some cases, the portion of bit cells of both the first memory array and the second memory array may be coupled to shared preamplifier circuitry.

公开(公告)号：US10573365B2

公开(公告)日：2020-02-25

申请号：US16251882

申请日：2019-01-18

Applicant: Everspin Technologies, Inc.

Inventor： Thomas Andre ,  Syed M. Alam

IPC: G11C11/16 ,  G06F11/10 ,  G11C11/4094 ,  G11C7/12 ,  G11C8/08 ,  G11C8/14

Abstract: In a spin-torque magnetic random access memory (MRAM) that includes local source lines, auto-booting of the word line is used to reduce power consumption by reusing charge already present from driving a plurality of bit lines during writing operations. Auto-booting is accomplished by first driving a global word line to a first voltage. Driving the global word line to a first voltage results in a second voltage passed to the word lines. Subsequent driving of the plurality of bit lines that are capacitively coupled to the word line causes the word line voltage to be increased to a level desired to allow sufficient current to flow through a selected memory cell to write information into the selected memory cell.

公开(公告)号：US10475497B2

公开(公告)日：2019-11-12

申请号：US16000071

申请日：2018-06-05

Applicant: EVERSPIN TECHNOLOGIES, INC.

Inventor： Syed M. Alam ,  Chitra Subramanian

IPC: G11C11/00 ,  G11C11/16 ,  G11C27/02

Abstract: Precharging circuits and techniques are presented for use with magnetic memory devices in order to speed up access to the memory cells for reading and writing. Including precharging in the sense amplifiers used to access the memory cells enables self-referenced read operations to be completed more quickly than is possible without precharging. Similarly, precharging can also be used in conjunction with write-back operations in order to allow the data state stored by magnetic tunnel junctions included in the memory cells to be changed more rapidly.

公开(公告)号：US10269405B2

公开(公告)日：2019-04-23

申请号：US15605508

申请日：2017-05-25

Applicant: EVERSPIN TECHNOLOGIES, INC.

Inventor： Thomas Andre ,  Dimitri Houssameddine ,  Syed M. Alam ,  Jon Slaughter ,  Chitra Subramanian

IPC: G11C11/00 ,  G11C11/16 ,  G06F12/0804

Abstract: A memory device is configured to identify a set of bit cells to be changed from a first state to a second state. In some examples, the memory device may apply a first voltage to the set of bit cells to change a least a first portion of the set of bit cells to the second state. In some cases, the memory device may also identify a second portion of the bit cells that remained in the first state following the application of the first voltage. In these cases, the memory device may apply a second voltage having a greater magnitude, duration, or both to the second portion of the set of bit cells in order to set the second portion of bit cells to the second state.

公开(公告)号：US10262713B2

公开(公告)日：2019-04-16

申请号：US15401235

申请日：2017-01-09

Applicant: Everspin Technologies, Inc.

Inventor： Jason Janesky ,  Syed M. Alam ,  Dimitri Houssameddine ,  Mark Deherrera

IPC: G11C11/56 ,  G11C11/16 ,  G11C29/12 ,  G11C29/02 ,  G11C29/50 ,  G11C17/16

Abstract: Techniques and circuits for testing and configuring bias voltage or bias current for write operations in memory devices are presented. Registers and nonvolatile storage is included on the memory devices for storing values used to control testing of the memory devices as well as for configuring parameters related to both testing and normal operation.

公开(公告)号：US10146601B2

公开(公告)日：2018-12-04

申请号：US14297386

申请日：2014-06-05

Applicant: Everspin Technologies, Inc.

Inventor： Jon Slaughter ,  Dimitri Houssameddine ,  Thomas Andre ,  Syed M. Alam

IPC: G06F11/00 ,  G06F11/07 ,  G11C11/16

Abstract: A method is provided for healing reset errors for a magnetic memory using destructive read with selective write-back, including for example, a self-referenced read of spin-torque bits in an MRAM. Memory cells are prepared for write back by one of identifying memory cells determined in error using an error correcting code and inverting the inversion bit for those memory cells determined in error; identifying memory cells determined in error using an error correcting code and resetting a portion of the memory cells to the first state; and resetting one or more memory cells to the first state.

公开(公告)号：US10141039B2

公开(公告)日：2018-11-27

申请号：US14495083

申请日：2014-09-24

Applicant: Everspin Technologies, Inc.

Inventor： Thomas Andre ,  Syed M. Alam

IPC: G06F12/08 ,  G11C11/16 ,  G06F12/0806 ,  G06F12/0879 ,  G11C7/10 ,  G11C7/22 ,  G11C7/12 ,  G11C11/4094 ,  G11C11/419 ,  G11C11/4091 ,  G11C11/56

Abstract: In some examples, a memory device is configured with a reduced command set and a variable burst length. In some instances, the variable burst length defines a page size associated with data to be loaded into a cache. In other instances, the variable burst length may be set on the fly per read/write command and, in some cases, the burst length may be utilized to define the page size associated with the read/write command.

公开(公告)号：US10037790B2

公开(公告)日：2018-07-31

申请号：US15452831

申请日：2017-03-08

Applicant: Everspin Technologies, Inc.

Inventor： Thomas Andre ,  Syed M. Alam

IPC: G11C11/16 ,  G11C7/12 ,  G11C7/08 ,  G06F12/0806 ,  G06F12/0879 ,  G11C7/10 ,  G11C7/22 ,  G11C11/4094 ,  G11C11/419 ,  G11C11/4091 ,  G11C11/56

CPC classification number: G11C11/1675 ,  G06F12/0806 ,  G06F12/0879 ,  G06F2212/62 ,  G11C7/1018 ,  G11C7/1045 ,  G11C7/12 ,  G11C7/22 ,  G11C11/16 ,  G11C11/1655 ,  G11C11/1657 ,  G11C11/1659 ,  G11C11/1673 ,  G11C11/1693 ,  G11C11/4091 ,  G11C11/4094 ,  G11C11/419 ,  G11C11/5607 ,  Y02D10/13

Abstract: In a spin-torque magnetic random access memory (MRAM) that includes local source lines, auto-booting of the word line is used to reduce power consumption by reusing charge already present from driving a plurality of bit lines during writing operations. Auto-booting is accomplished by first driving the word line to a first word line voltage. After such driving, the word line isolated. Subsequent driving of the plurality of bit lines that are capacitively coupled to the word line causes the word line voltage to be increased to a level desired to allow sufficient current to flow through a selected memory cell to write information into the selected memory cell. Additional embodiments include the use of a supplemental voltage provider that is able to further boost or hold the isolated word line at the needed voltage level.