Invention Grant
US09553092B2 Alternative threshold voltage scheme via direct metal gate patterning for high performance CMOS FinFETs
有权
通过用于高性能CMOS FinFET的直接金属栅极图案化的替代阈值电压方案
- Patent Title: Alternative threshold voltage scheme via direct metal gate patterning for high performance CMOS FinFETs
- Patent Title (中): 通过用于高性能CMOS FinFET的直接金属栅极图案化的替代阈值电压方案
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Application No.: US14738288Application Date: 2015-06-12
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Publication No.: US09553092B2Publication Date: 2017-01-24
- Inventor: Ruqiang Bao , Siddarth A. Krishnan , Unoh Kwon , Keith Kwong Hon Wong
- Applicant: GLOBALFOUNDRIES INC.
- Applicant Address: KY Grand Cayman
- Assignee: GLOBALFOUNDRIES INC.
- Current Assignee: GLOBALFOUNDRIES INC.
- Current Assignee Address: KY Grand Cayman
- Agency: Scully, Scott, Murphy & Presser, P.C.
- Main IPC: H01L27/092
- IPC: H01L27/092 ; H01L29/49 ; H01L21/3213 ; H01L21/8238 ; H01L29/66
Abstract:
Multiple gate stack portions are formed in a gate cavity by direct metal gate patterning to provide FinFETs having different threshold voltages. The different threshold voltages are obtained by selectively incorporating metal layers with different work functions in different gate stack portions.
Public/Granted literature
- US20160365347A1 ALTERNATIVE THRESHOLD VOLTAGE SCHEME VIA DIRECT METAL GATE PATTERNING FOR HIGH PERFORMANCE CMOS FinFETs Public/Granted day:2016-12-15
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