公开(公告)号：US10361132B2

公开(公告)日：2019-07-23

申请号：US15476158

申请日：2017-03-31

Applicant: GLOBALFOUNDRIES INC.

Inventor： Ruqiang Bao ,  Takashi Ando ,  Aritra Dasgupta ,  Kai Zhao ,  Unoh Kwon ,  Siddarth A. Krishnan

IPC: H01L21/02 ,  H01L21/28 ,  H01L29/49 ,  H01L29/51 ,  H01L21/285 ,  H01L21/311 ,  H01L27/092 ,  H01L21/8238

Abstract: The disclosure relates to semiconductor structures and, more particularly, to structures with thinned dielectric material and methods of manufacture. The method includes depositing a high-k dielectric on a substrate. The method further includes depositing a titanium nitride film directly on the high-k while simultaneously etching the high-k dielectric.

公开(公告)号：US10192822B2

公开(公告)日：2019-01-29

申请号：US14623115

申请日：2015-02-16

Applicant: GLOBALFOUNDRIES INC.

Inventor： Domingo A. Ferrer ,  Kriteshwar K. Kohli ,  Siddarth A. Krishnan ,  Joseph F. Shepard, Jr. ,  Keith Kwong Hon Wong

IPC: H01L27/112 ,  H01L23/525 ,  H01L23/522 ,  H01L21/768

Abstract: A method for forming a precision resistor or an e-fuse structure where tungsten silicon is used. The tungsten silicon layer is modified by implanting nitrogen into the structure.

公开(公告)号：US09960233B2

公开(公告)日：2018-05-01

申请号：US15600837

申请日：2017-05-22

Applicant: GLOBALFOUNDRIES INC.

Inventor： Siddarth A. Krishnan ,  Unoh Kwon ,  Vijay Narayanan ,  Jeffrey W. Sleight

IPC: H01L29/06 ,  H01L29/66 ,  H01L29/739 ,  H01L29/417 ,  H01L29/423 ,  H01L29/775 ,  H01L29/45 ,  H01L29/165 ,  H01L29/205

CPC classification number: H01L29/0673 ,  H01L29/083 ,  H01L29/165 ,  H01L29/205 ,  H01L29/41758 ,  H01L29/42356 ,  H01L29/45 ,  H01L29/458 ,  H01L29/66356 ,  H01L29/66469 ,  H01L29/66553 ,  H01L29/7391 ,  H01L29/775

Abstract: After forming a buried nanowire segment surrounded by a gate structure located on a substrate, an epitaxial source region is grown on a first end of the buried nanowire segment while covering a second end of the buried nanowire segment and the gate structure followed by growing an epitaxial drain region on the second end of the buried nanowire segment while covering the epitaxial source region and the gate structure. The epitaxial source region includes a first semiconductor material and dopants of a first conductivity type, while the epitaxial drain region includes a first semiconductor material different from the first semiconductor material and dopants of a second conductivity type opposite the first conductivity type.

公开(公告)号：US09679810B1

公开(公告)日：2017-06-13

申请号：US15041203

申请日：2016-02-11

Applicant: GLOBALFOUNDRIES INC.

Inventor： Joyeeta Nag ,  Shishir K. Ray ,  Andrew H. Simon ,  Oleg Gluschenkov ,  Siddarth A. Krishnan ,  Michael P. Chudzik

IPC: H01L23/48 ,  H01L21/768 ,  H01L23/522

CPC classification number: H01L23/5283 ,  H01L21/2885 ,  H01L21/76877 ,  H01L21/76883 ,  H01L23/53238 ,  H01L23/53252

Abstract: An aspect of the disclosure is directed to a method of forming an interconnect for use in an integrated circuit. The method comprises: forming an opening in a dielectric layer on a substrate; filling the opening with a metal such that an overburden outside of the opening is created; subjecting the metal to a microwave energy dose such that atoms from the overburden migrate to within the opening; and planarizing the metal to a top surface of the opening to remove the overburden, thereby forming the interconnect.

公开(公告)号：US20160308025A1

公开(公告)日：2016-10-20

申请号：US14685944

申请日：2015-04-14

Applicant: GLOBALFOUNDRIES INC.

Inventor： Michael P. Chudzik ,  Siddarth A. Krishnan ,  Unoh Kwon ,  Vijay Narayanan ,  Jeffrey W. Sleight

IPC: H01L29/66 ,  H01L21/02 ,  H01L29/20 ,  H01L29/88 ,  H01L29/78

CPC classification number: H01L29/66545 ,  H01L21/02538 ,  H01L21/02617 ,  H01L29/0657 ,  H01L29/20 ,  H01L29/267 ,  H01L29/66151 ,  H01L29/66356 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/7391 ,  H01L29/785 ,  H01L29/88

Abstract: A semiconductor structure includes a substrate and an intrinsic replacement channel. A tunneling field effect transistor (TFET) fin may be formed by the intrinsic replacement channel, a p-fin and an n-fin formed upon the substrate. The p-fin may serve as the source of the TFET and the n-fin may serve as the drain of the TFET. The replacement channel may be formed in place of a sacrificial channel of a diode fin that includes the p-fin, the n-fin, and the sacrificial channel at the p-fin and n-fin junction.

Abstract translation: 半导体结构包括衬底和固有置换通道。 隧道场效应晶体管（TFET）鳍可以由本征替换沟道，形成在衬底上的p鳍和n鳍形成。 p鳍可以用作TFET的源极，并且n鳍可以用作TFET的漏极。 可以形成替代通道来代替在p鳍和n鳍结上包括p鳍，n鳍和牺牲沟道的二极管鳍片的牺牲通道。

公开(公告)号：US09412658B2

公开(公告)日：2016-08-09

申请号：US14490792

申请日：2014-09-19

Applicant: International Business Machines Corporation ,  GLOBALFOUNDRIES Inc.

Inventor： Oleg Gluschenkov ,  Siddarth A. Krishnan ,  Joyeeta Nag ,  Andrew H. Simon ,  Shishir Ray

IPC: H01L23/52 ,  H01L23/522 ,  H01L21/768 ,  H01L23/532 ,  H01L21/4763

CPC classification number: H01L21/76894 ,  H01L21/76834 ,  H01L21/76843 ,  H01L21/76867 ,  H01L21/76883 ,  H01L23/53228 ,  H01L23/53233 ,  H01L23/53238 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/01029 ,  H01L2924/00

Abstract: In-situ melting and crystallization of sealed cooper wires can be performed by means of laser annealing for a duration of nanoseconds. The intensity of the laser irradiation is selected such that molten copper wets interconnect interfaces, thereby forming an interfacial bonding arrangement that increases specular scattering of electrons. Nanosecond-scale temperature quenching preserves the formed interfacial bonding. At the same time, the fast crystallization process of sealed copper interconnects results in large copper grains, typically larger than 80 nm in lateral dimensions, on average. A typical duration of the annealing process is from about 10's to about 100's of nanoseconds. There is no degradation to interlayer low-k dielectric material despite the high anneal temperature due to ultra short duration that prevents collective motion of atoms within the dielectric material.

Abstract translation: 密封铜线的原位熔融和结晶可以通过激光退火进行纳秒的持续时间。 选择激光照射的强度，使得熔融铜浸润互连界面，从而形成增加电子的镜面散射的界面结合装置。 纳秒级温度淬火保持形成的界面结合。 同时，密封铜互连的快速结晶过程平均导致大的铜晶粒，通常大于80nm的横向尺寸。 退火过程的典型持续时间为约10秒至约100秒的纳秒。 尽管由于超短时间的高退火温度，层间低k介电材料没有劣化，从而防止原子在电介质材料内的集体运动。

公开(公告)号：US20170263707A1

公开(公告)日：2017-09-14

申请号：US15600837

申请日：2017-05-22

Applicant: GLOBALFOUNDRIES INC.

Inventor： Siddarth A. Krishnan ,  Unoh Kwon ,  Vijay Narayanan ,  Jeffrey W. Sleight

IPC: H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/417

CPC classification number: H01L29/0673 ,  H01L29/083 ,  H01L29/165 ,  H01L29/205 ,  H01L29/41758 ,  H01L29/42356 ,  H01L29/45 ,  H01L29/458 ,  H01L29/66356 ,  H01L29/66469 ,  H01L29/66553 ,  H01L29/7391 ,  H01L29/775

Abstract: After forming a buried nanowire segment surrounded by a gate structure located on a substrate, an epitaxial source region is grown on a first end of the buried nanowire segment while covering a second end of the buried nanowire segment and the gate structure followed by growing an epitaxial drain region on the second end of the buried nanowire segment while covering the epitaxial source region and the gate structure. The epitaxial source region includes a first semiconductor material and dopants of a first conductivity type, while the epitaxial drain region includes a first semiconductor material different from the first semiconductor material and dopants of a second conductivity type opposite the first conductivity type.

公开(公告)号：US09691662B2

公开(公告)日：2017-06-27

申请号：US15338894

申请日：2016-10-31

Applicant: GLOBALFOUNDRIES INC.

Inventor： Takashi Ando ,  Min Dai ,  Balaji Kannan ,  Siddarth A. Krishnan ,  Unoh Kwon

IPC: H01L21/8234 ,  H01L29/49 ,  H01L21/8238 ,  H01L27/092 ,  H01L21/324 ,  H01L27/088 ,  H01L29/78

CPC classification number: H01L21/823412 ,  H01L21/324 ,  H01L21/823431 ,  H01L21/82345 ,  H01L21/823462 ,  H01L21/823842 ,  H01L27/088 ,  H01L27/0886 ,  H01L27/092 ,  H01L27/0924 ,  H01L29/4966 ,  H01L29/785

Abstract: Selective deposition of a silicon-germanium surface layer on semiconductor surfaces can be employed to provide two types of channel regions for field effect transistors. Anneal of an adjustment oxide material on a stack of a silicon-based gate dielectric and a high dielectric constant (high-k) gate dielectric can be employed to form an interfacial adjustment oxide layer contacting a subset of channel regions. Oxygen deficiency can be induced in portions of the high-k dielectric layer overlying the interfacial adjustment oxide layer by deposition of a first work function metallic material layer and a capping layer and a subsequent anneal. Oxygen deficiency can be selectively removed by physically exposing portions of the high-k dielectric layer. A second work function metallic material layer and a gate conductor layer can be deposited and planarized to form gate electrodes that provide multiple effective work functions.

公开(公告)号：US20170110539A1

公开(公告)日：2017-04-20

申请号：US14887572

申请日：2015-10-20

Applicant: GLOBALFOUNDRIES INC.

Inventor： Siddarth A. Krishnan ,  Unoh Kwon ,  Vijay Narayanan ,  Jeffrey W. Sleight

IPC: H01L29/06 ,  H01L29/775 ,  H01L29/66 ,  H01L29/417 ,  H01L29/423

CPC classification number: H01L29/0673 ,  H01L29/083 ,  H01L29/165 ,  H01L29/205 ,  H01L29/41758 ,  H01L29/42356 ,  H01L29/45 ,  H01L29/458 ,  H01L29/66356 ,  H01L29/66469 ,  H01L29/66553 ,  H01L29/7391 ,  H01L29/775

Abstract: After forming a buried nanowire segment surrounded by a gate structure located on a substrate, an epitaxial source region is grown on a first end of the buried nanowire segment while covering a second end of the buried nanowire segment and the gate structure followed by growing an epitaxial drain region on the second end of the buried nanowire segment while covering the epitaxial source region and the gate structure. The epitaxial source region includes a first semiconductor material and dopants of a first conductivity type, while the epitaxial drain region includes a first semiconductor material different from the first semiconductor material and dopants of a second conductivity type opposite the first conductivity type.

公开(公告)号：US09484427B2

公开(公告)日：2016-11-01

申请号：US14320831

申请日：2014-07-01

Applicant: GLOBALFOUNDRIES INC.

Inventor： Takashi Ando ,  Min Dai ,  Balaji Kannan ,  Siddarth A. Krishnan ,  Unoh Kwon

IPC: H01L29/49 ,  H01L21/8234 ,  H01L21/8238 ,  H01L27/092 ,  H01L27/088 ,  H01L29/78

CPC classification number: H01L21/823412 ,  H01L21/324 ,  H01L21/823431 ,  H01L21/82345 ,  H01L21/823462 ,  H01L21/823842 ,  H01L27/088 ,  H01L27/0886 ,  H01L27/092 ,  H01L27/0924 ,  H01L29/4966 ,  H01L29/785

Abstract: Selective deposition of a silicon-germanium surface layer on semiconductor surfaces can be employed to provide two types of channel regions for field effect transistors. Anneal of an adjustment oxide material on a stack of a silicon-based gate dielectric and a high dielectric constant (high-k) gate dielectric can be employed to form an interfacial adjustment oxide layer contacting a subset of channel regions. Oxygen deficiency can be induced in portions of the high-k dielectric layer overlying the interfacial adjustment oxide layer by deposition of a first work function metallic material layer and a capping layer and a subsequent anneal. Oxygen deficiency can be selectively removed by physically exposing portions of the high-k dielectric layer. A second work function metallic material layer and a gate conductor layer can be deposited and planarized to form gate electrodes that provide multiple effective work functions.

Abstract translation: 硅 - 锗表面层在半导体表面上的选择性沉积可用于为场效应晶体管提供两种类型的沟道区。 在硅基栅极电介质和高介电常数（高k）栅极电介质的堆叠上的调整氧化物材料的退火可以用于形成接触通道区域子集的界面调整氧化物层。 通过沉积第一功函数金属材料层和封盖层和随后的退火，可以在覆盖界面调整氧化物层的高k电介质层的部分中诱导氧缺乏。 可以通过物理暴露高k电介质层的部分来选择性地去除氧缺乏。 可以将第二功函数金属材料层和栅极导体层沉积并平坦化以形成提供多个有效功函数的栅电极。