Invention Grant
- Patent Title: Timing violation handling in a synchronous interface memory
- Patent Title (中): 同步接口内存中的定时违规处理
-
Application No.: US14954587Application Date: 2015-11-30
-
Publication No.: US09558799B2Publication Date: 2017-01-31
- Inventor: Marco Ferrario , Christophe Vincent Antoine Laurent , Francesco Mastroianni
- Applicant: Micron Technology, Inc.
- Applicant Address: US ID Boise
- Assignee: Micron Technology, Inc.
- Current Assignee: Micron Technology, Inc.
- Current Assignee Address: US ID Boise
- Agency: Schwegman Lundberg & Woessner, P.A.
- Main IPC: G11C8/12
- IPC: G11C8/12 ; G11C13/00 ; G11C7/10 ; G11C7/22 ; G11C8/18 ; G11C11/21 ; G06F12/08 ; G11C16/04
Abstract:
A memory device includes an operation having a phase to provide an upper row address from a row address buffer, a phase to combine the upper row address with a lower row address to select data for a row data buffer, and a phase to output the data from the row data buffer, wherein an activate command starts and following activate commands are ignored until a preset time has elapsed.
Public/Granted literature
- US20160086662A1 TIMING VIOLATION HANDLING IN A SYNCHRONOUS INTERFACE MEMORY Public/Granted day:2016-03-24
Information query
