-
公开(公告)号：US20240232095A9
公开(公告)日：2024-07-11
申请号：US17972493
申请日：2022-10-24
IPC分类号： G06F12/0891
CPC分类号： G06F12/0891 , G06F2212/305
摘要： Systems, methods, and apparatus for a memory device that stores a scrub list in a cache used to reduce data traffic to and from a memory array. In one approach, the cache merges the scrub list with cache data. Data in the scrub list can be identified and distinguished from the cache data by adding a one-bit scrub flag to each data entry in the merged cache. In this merged approach, the cache data shares the same memory as the scrub list. Read data that has an error is saved temporarily in this merged cache until the correct value for the data is written back into the memory array.
-
公开(公告)号：US11811424B2
公开(公告)日：2023-11-07
申请号：US17222660
申请日：2021-04-05
CPC分类号： H03M13/2906 , G06F11/1076 , G11C15/04
摘要： Methods, systems, and devices for fixed weight codewords for ternary memory cells are described. A memory device may generate a codeword from a set of data bits and invert a portion of the codeword so that the codeword is associated with a target distribution of programmable states. After inverting the portion of the codeword, the memory device store the codeword in a set of ternary cells according to a coding scheme. The memory device may read the codeword from the set of ternary cells and select one or more reference voltages for the set of ternary cells based on the target distribution for the codeword and the states of the ternary cells.
-
公开(公告)号：US11567831B2
公开(公告)日：2023-01-31
申请号：US16940766
申请日：2020-07-28
摘要： Methods, systems, and devices for generating a balanced codeword protected by an error correction code are described. A memory device receives data bits for storage. Based on the data bits, the memory device generates a codeword that includes the data bits, parity bits, and placeholder bits. The memory device balances the codeword by inverting one or more packets of the codeword. After balancing the codeword, the memory device stores at least a portion of the codeword in memory so that a later operation or a decoding process reveals the packets that were inverted as part of the balancing process. Accordingly, the memory device is able to re-invert the appropriate packets to recover the original data bits.
-
公开(公告)号：US20220415426A1
公开(公告)日：2022-12-29
申请号：US17361419
申请日：2021-06-29
摘要： Methods, systems, and devices for shared error correction coding (ECC) circuitry are described. For example, a memory device configured with shared ECC circuitry may be configured to receive data at the shared circuitry from either a host device or a set of memory cells of the memory device. The shared circuitry may be configured to generate a set of multiple syndromes associated with a cyclic error correction code, based on the received data. As part of an encoding process, an encoder circuit may generate a set of parity bits based on the generated syndromes. As part of a decoding process, a decoder circuit may generate an error vector for decoding the received data, based on the generated syndromes. The decoder circuit may also correct one or more errors in the received data based on generating the error vector.
-
公开(公告)号：US20220253237A1
公开(公告)日：2022-08-11
申请号：US17677586
申请日：2022-02-22
IPC分类号： G06F3/06
摘要： Methods, systems, and devices related to balancing data are described. Data may be communicated using an original set of bits that may be partitioned into segments. Each of the original set of bits may have a first value or a second value, where a weight of the original set of bits may be based on a quantity of the set of bits that have the first value. If the weight of the original set of bits is outside of a target weight range, a different, encoded set of bits may be used to represent the data, the encoded set of bits having a weight within the target weight range. The encoded set of bits may be identified based an inversion of the original set of bits in a one-at-a-time and cumulative fashion. The encoded set of bits may be stored in place of the original set of bits.
-
公开(公告)号：US11170850B2
公开(公告)日：2021-11-09
申请号：US17130210
申请日：2020-12-22
摘要： Methods, systems, and apparatus that support efficient utilization of die area for cross-point memory architecture are described. A memory array may include active memory cells overlying each portion of the substrate that includes certain types of support circuitry, such as decoders and sense amplifiers. Boundary tiles, which may be portions of an array having a different configuration from other portions of the array, may be positioned on one side of an array of memory tiles. The boundary tiles may include support components to access both memory cells of neighboring memory tiles and memory cells overlying the boundary tiles. Column lines and column line decoders may be integrated as part of a boundary tile. Access lines, such as row lines may be truncated or omitted at or near borders of the memory portion of the memory device.
-
公开(公告)号：US20210342090A1
公开(公告)日：2021-11-04
申请号：US16865163
申请日：2020-05-01
IPC分类号： G06F3/06
摘要： Methods, systems, and devices related to balancing data are described. Data may be communicated using an original set of bits that may be partitioned into segments. Each of the original set of bits may have a first value or a second value, where a weight of the original set of bits may be based on a quantity of the set of bits that have the first value. If the weight of the original set of bits is outside of a target weight range, a different, encoded set of bits may be used to represent the data, the encoded set of bits having a weight within the target weight range. The encoded set of bits may be identified based an inversion of the original set of bits in a one-at-a-time and cumulative fashion. The encoded set of bits may be stored in place of the original set of bits.
-
公开(公告)号：US20210183441A1
公开(公告)日：2021-06-17
申请号：US17130210
申请日：2020-12-22
IPC分类号： G11C13/00
摘要： Methods, systems, and apparatus that support efficient utilization of die area for cross-point memory architecture are described. A memory array may include active memory cells overlying each portion of the substrate that includes certain types of support circuitry, such as decoders and sense amplifiers. Boundary tiles, which may be portions of an array having a different configuration from other portions of the array, may be positioned on one side of an array of memory tiles. The boundary tiles may include support components to access both memory cells of neighboring memory tiles and memory cells overlying the boundary tiles. Column lines and column line decoders may be integrated as part of a boundary tile. Access lines, such as row lines may be truncated or omitted at or near borders of the memory portion of the memory device.
-
公开(公告)号：US20210011645A1
公开(公告)日：2021-01-14
申请号：US16508729
申请日：2019-07-11
IPC分类号： G06F3/06 , G11C11/22 , G11C11/408 , G11C11/4091 , G06F11/10 , G11C29/52
摘要： Methods, systems, and devices for circuit partitioning for a memory device are described. In one example, a memory device may include a set of memory tiles that each include a respective array of memory cells (e.g., in an array level or layer). Each of the memory tiles may include a respective circuit level or layer associated with circuitry configured to operate the respective array of memory cells. The memory device may also include circuitry for communicating data between the memory cells of the set of memory tiles and an input/output component. Aspects of the circuitry for communicating the data may be subdivided into repeatable blocks each configured to communicate one or more bits, and the repeatable blocks and other aspects of the circuitry for communicating the data is distributed across the circuit layer of two or more of the set of memory tiles.
-
公开(公告)号：US10510407B2
公开(公告)日：2019-12-17
申请号：US16405617
申请日：2019-05-07
摘要： Methods, systems, and apparatus that support efficient utilization of die area for cross-point memory architecture are described. A memory array may include active memory cells overlying each portion of the substrate that includes certain types of support circuitry, such as decoders and sense amplifiers. Boundary tiles, which may be portions of an array having a different configuration from other portions of the array, may be positioned on one side of an array of memory tiles. The boundary tiles may include support components to access both memory cells of neighboring memory tiles and memory cells overlying the boundary tiles. Column lines and column line decoders may be integrated as part of a boundary tile. Access lines, such as row lines may be truncated or omitted at or near borders of the memory portion of the memory device.
-
-
-
-
-
-
-
-
-
搜索结果
81 条记录 (耗时 0.029 秒)
