Invention Grant
- Patent Title: Wafer back-side polishing system and method for integrated circuit device manufacturing processes
- Patent Title (中): 晶圆背面抛光系统及集成电路元件制造工艺的方法
-
Application No.: US15060807Application Date: 2016-03-04
-
Publication No.: US09559021B2Publication Date: 2017-01-31
- Inventor: Shen-Nan Lee , Teng-Chun Tsai , Hsin-Hsien Lu , Chang-Sheng Lin , Kuo-Cheng Lien , Kuo-Yin Lin , Wen-Kuei Liu , Yu-Wei Chou
- Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
- Applicant Address: TW Hsin-Chu
- Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee Address: TW Hsin-Chu
- Agency: Eschweiler & Associates, LLC
- Main IPC: H01L21/66
- IPC: H01L21/66 ; H01L21/02 ; H01L21/306 ; B24B9/06 ; B24B7/22 ; B24B21/00

Abstract:
A wafer polishing process includes polishing a central area on the back side of a wafer, polishing a peripheral area on the back side of the wafer, buffing the central area, and buffing the peripheral area. The process can significantly reduce scratch-related wafer breakage, can correct focus spots on wafers, and can replace cleaning processes that use chemical etchants. Polishing and buffing can include polishing and buffing the bevel region. Further improvements include polishing with abrasive pads having a soft backing, polishing or buffing with pads having relatively soft abrasive particles, polishing or buffing with abrasive pads made from abrasive particles that have been sorted and selected for regularity of shape, irrigating the surface being polished or buffed with an aqueous solution that includes a friction-reducing agent, and buffing with abrasive pads having 20k or finer grit or non-abrasive pads.
Public/Granted literature
- US20160190023A1 WAFER BACK-SIDE POLISHING SYSTEM AND METHOD FOR INTEGRATED CIRCUIT DEVICE MANUFACTURING PROCESSES Public/Granted day:2016-06-30
Information query
IPC分类: