公开(公告)号：US20150263132A1

公开(公告)日：2015-09-17

申请号：US14208697

申请日：2014-03-13

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Wen-Kuei Liu ,  Teng-Chun Tsai ,  Kuo-Yin Lin ,  Shen-Nan Lee ,  Yu-Wei Chou ,  Kuo-Cheng Lien ,  Chang-Sheng Lin ,  Chih-Chang Hung ,  Yung-Cheng Lu

IPC分类号： H01L29/66 ,  H01L21/311 ,  H01L21/02 ,  H01L21/3105

CPC分类号： H01L21/31055 ,  H01L21/02282 ,  H01L21/28123 ,  H01L21/3086 ,  H01L21/31058 ,  H01L21/31116 ,  H01L21/31138 ,  H01L21/31144 ,  H01L21/32136 ,  H01L21/823821 ,  H01L21/845 ,  H01L29/0692 ,  H01L29/66545 ,  H01L29/66795

摘要： An IC device manufacturing process effectuates a planar recessing of material that initially varies in height across a substrate. The method includes forming a bottom anti-reflective coating (BARC), baking to induce cross-linking in the BARC, CMP to remove a first portion of the BARC and form a planar surface, then plasma etching to effectuate a planar recessing of the BARC. The plasma etching can have a low selectivity between the BARC and the material being recessed, whereby the BARC and the material are recessed simultaneously. Any of the material above a certain height is removed. Structures that are substantially below that certain height can be protected from contamination and left intact. The method can be particularly effective when an abrasive used during CMP forms ester linkages with the BARC.

摘要翻译： IC器件制造工艺实现了最初在衬底上高度变化的材料的平面凹陷。 该方法包括形成底部抗反射涂层（BARC），烘烤以在BARC，CMP中引发交联以除去BARC的第一部分并形成平坦表面，然后进行等离子体蚀刻以实现BARC的平面凹陷 。 等离子体蚀刻可以在BARC和被凹入的材料之间具有低选择性，由此BARC和材料同时凹陷。 任何高于一定高度的材料都被去除。 可以保护基本上低于该特定高度的结构免受污染并保持不变。 当CMP中使用的研磨剂与BARC形成酯键时，该方法可以是特别有效的。

公开(公告)号：US11011385B2

公开(公告)日：2021-05-18

申请号：US15686922

申请日：2017-08-25

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Wen-Kuei Liu ,  Teng-Chun Tsai ,  Kuo-Yin Lin ,  Shen-Nan Lee ,  Yu-Wei Chou ,  Kuo-Cheng Lien ,  Chang-Sheng Lin ,  Chih-Chang Hung ,  Yung-Cheng Lu

IPC分类号： H01L21/3105 ,  H01L21/84 ,  H01L21/28 ,  H01L21/3213 ,  H01L21/027 ,  H01L21/311 ,  H01L21/8238 ,  H01L29/66

摘要： A method of manufacturing an integrated circuit device is provided. A first feature, which has a first susceptibility to damage by chemical mechanical processing (CMP), is formed at a first height as measured from an upper surface of the substrate. A second feature, which has a second susceptibility to damage by the CMP, is formed at a second height as measured from the upper surface of the substrate and is laterally spaced from the first feature by a recess. The second height is greater than the first height, and the second susceptibility is less than the first susceptibility. A sacrificial coating is formed in the recess over an uppermost surface of the first feature. CMP is performed to remove a first portion of the sacrificial coating and expose an upper surface of the second feature while leaving a second portion of the sacrificial coating in place over the first feature.

公开(公告)号：US09852899B2

公开(公告)日：2017-12-26

申请号：US15407893

申请日：2017-01-17

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Shen-Nan Lee ,  Teng-Chun Tsai ,  Hsin-Hsien Lu ,  Chang-Sheng Lin ,  Kuo-Cheng Lien ,  Kuo-Yin Lin ,  Wen-Kuei Liu ,  Yu-Wei Chou

IPC分类号： H01L21/02 ,  H01L21/66 ,  H01L21/67 ,  B24B7/22 ,  B24B9/06

CPC分类号： H01L21/0209 ,  B24B7/228 ,  B24B9/065 ,  B24B21/002 ,  H01L21/02043 ,  H01L21/02057 ,  H01L21/02087 ,  H01L21/02096 ,  H01L21/30625 ,  H01L21/67092 ,  H01L21/67288 ,  H01L22/12 ,  H01L22/20

摘要： Some embodiments are directed to a wafer polishing tool. The wafer polishing tool includes a first polisher, a second polisher downstream of the first polisher, a third polisher downstream of the second polisher, and a fourth polisher downstream of the third polisher. The first polisher receives a wafer having a front side and a back side with integrated circuit component devices disposed on the front side of the wafer, and polishes a center region on the back side of the wafer. The second polisher receives the wafer via transporting equipment and buffs the center region of the back side of the wafer. The third polisher receives the wafer via the transporting equipment and polishes a back side edge region of the wafer. The fourth polisher receives the wafer via the transporting equipment and buffs the back side edge region of the wafer.

公开(公告)号：US20160172209A1

公开(公告)日：2016-06-16

申请号：US15047793

申请日：2016-02-19

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Wen-Kuei Liu ,  Teng-Chun Tsai ,  Kuo-Yin Lin ,  Shen-Nan Lee ,  Yu-Wei Chou ,  Kuo-Cheng Lien ,  Chang-Sheng Lin ,  Chih-Chang Hung ,  Yung-Cheng Lu

IPC分类号： H01L21/3105 ,  H01L21/3213 ,  H01L21/311 ,  H01L21/027 ,  H01L21/28

CPC分类号： H01L21/31055 ,  H01L21/0273 ,  H01L21/0274 ,  H01L21/28008 ,  H01L21/31058 ,  H01L21/31116 ,  H01L21/31133 ,  H01L21/31138 ,  H01L21/3213 ,  H01L21/32139 ,  H01L21/823821 ,  H01L21/845 ,  H01L29/66545

摘要： An IC device manufacturing process effectuates a planar recessing of material that initially varies in height across a substrate. The method includes forming a polymer coating, CMP to form a planar surface, then plasma etching to effectuate a planar recessing of the polymer coating. The material can be recessed together with the polymer coating, or subsequently with the recessed polymer coating providing a mask. Any of the material above a certain height is removed. Structures that are substantially below that certain height can be protected from contamination and left intact. The polymer can be a photoresist. The polymer can be provided with suitable adhesion and uniformity for the CMP process through a two-step baking process and by exhausting the baking chamber from below the substrate.

公开(公告)号：US09748109B2

公开(公告)日：2017-08-29

申请号：US15047793

申请日：2016-02-19

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Wen-Kuei Liu ,  Teng-Chun Tsai ,  Kuo-Yin Lin ,  Shen-Nan Lee ,  Yu-Wei Chou ,  Kuo-Cheng Lien ,  Chang-Sheng Lin ,  Chih-Chang Hung ,  Yung-Cheng Lu

IPC分类号： H01L21/3105 ,  H01L21/027 ,  H01L21/311 ,  H01L21/28 ,  H01L21/3213 ,  H01L21/8238 ,  H01L21/84 ,  H01L29/66

CPC分类号： H01L21/31055 ,  H01L21/0273 ,  H01L21/0274 ,  H01L21/28008 ,  H01L21/31058 ,  H01L21/31116 ,  H01L21/31133 ,  H01L21/31138 ,  H01L21/3213 ,  H01L21/32139 ,  H01L21/823821 ,  H01L21/845 ,  H01L29/66545

摘要： An IC device manufacturing process effectuates a planar recessing of material that initially varies in height across a substrate. The method includes forming a polymer coating, CMP to form a planar surface, then plasma etching to effectuate a planar recessing of the polymer coating. The material can be recessed together with the polymer coating, or subsequently with the recessed polymer coating providing a mask. Any of the material above a certain height is removed. Structures that are substantially below that certain height can be protected from contamination and left intact. The polymer can be a photoresist. The polymer can be provided with suitable adhesion and uniformity for the CMP process through a two-step baking process and by exhausting the baking chamber from below the substrate.

公开(公告)号：US09559021B2

公开(公告)日：2017-01-31

申请号：US15060807

申请日：2016-03-04

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Shen-Nan Lee ,  Teng-Chun Tsai ,  Hsin-Hsien Lu ,  Chang-Sheng Lin ,  Kuo-Cheng Lien ,  Kuo-Yin Lin ,  Wen-Kuei Liu ,  Yu-Wei Chou

IPC分类号： H01L21/66 ,  H01L21/02 ,  H01L21/306 ,  B24B9/06 ,  B24B7/22 ,  B24B21/00

CPC分类号： H01L21/0209 ,  B24B7/228 ,  B24B9/065 ,  B24B21/002 ,  H01L21/02043 ,  H01L21/02057 ,  H01L21/02087 ,  H01L21/02096 ,  H01L21/30625 ,  H01L21/67092 ,  H01L21/67288 ,  H01L22/12 ,  H01L22/20

摘要： A wafer polishing process includes polishing a central area on the back side of a wafer, polishing a peripheral area on the back side of the wafer, buffing the central area, and buffing the peripheral area. The process can significantly reduce scratch-related wafer breakage, can correct focus spots on wafers, and can replace cleaning processes that use chemical etchants. Polishing and buffing can include polishing and buffing the bevel region. Further improvements include polishing with abrasive pads having a soft backing, polishing or buffing with pads having relatively soft abrasive particles, polishing or buffing with abrasive pads made from abrasive particles that have been sorted and selected for regularity of shape, irrigating the surface being polished or buffed with an aqueous solution that includes a friction-reducing agent, and buffing with abrasive pads having 20k or finer grit or non-abrasive pads.

摘要翻译： 晶片抛光工艺包括抛光晶片背面的中心区域，抛光晶片背面的周边区域，抛光中心区域，以及抛光周边区域。 该过程可以显着减少划痕相关的晶片断裂，可以校正晶片上的焦点，并可以替代使用化学蚀刻剂的清洗工艺。 抛光和抛光可以包括抛光和抛光斜面区域。 进一步的改进包括用具有柔软背衬的研磨垫，抛光或抛光，具有相对较软的磨料颗粒的垫，抛光或抛光，其中由磨料颗粒制成的研磨垫已被分选并选择成规则形状，冲洗正被抛光的表面 用包含减摩剂的水溶液抛光，并用具有20k或更细砂粒或非研磨垫的研磨垫进行抛光。

公开(公告)号：US20170352548A1

公开(公告)日：2017-12-07

申请号：US15686922

申请日：2017-08-25

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Wen-Kuei Liu ,  Teng-Chun Tsai ,  Kuo-Yin Lin ,  Shen-Nan Lee ,  Yu-Wei Chou ,  Kuo-Cheng Lien ,  Chang-Sheng Lin ,  Chih-Chang Hung ,  Yung-Cheng Lu

IPC分类号： H01L21/3105 ,  H01L21/84 ,  H01L21/28 ,  H01L21/3213 ,  H01L21/027 ,  H01L21/311 ,  H01L29/66 ,  H01L21/8238

CPC分类号： H01L21/31055 ,  H01L21/0273 ,  H01L21/0274 ,  H01L21/28008 ,  H01L21/31058 ,  H01L21/31116 ,  H01L21/31133 ,  H01L21/31138 ,  H01L21/3213 ,  H01L21/32139 ,  H01L21/823821 ,  H01L21/845 ,  H01L29/66545

摘要： A method of manufacturing an integrated circuit device is provided. A first feature, which has a first susceptibility to damage by chemical mechanical processing (CMP), is formed at a first height as measured from an upper surface of the substrate. A second feature, which has a second susceptibility to damage by the CMP, is formed at a second height as measured from the upper surface of the substrate and is laterally spaced from the first feature by a recess. The second height is greater than the first height, and the second susceptibility is less than the first susceptibility. A sacrificial coating is formed in the recess over an uppermost surface of the first feature. CMP is performed to remove a first portion of the sacrificial coating and expose an upper surface of the second feature while leaving a second portion of the sacrificial coating in place over the first feature.

公开(公告)号：US20160099157A1

公开(公告)日：2016-04-07

申请号：US14967741

申请日：2015-12-14

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Wen-Kuei Liu ,  Teng-Chun Tsai ,  Kuo-Yin Lin ,  Shen-Nan Lee ,  Yu-Wei Chou ,  Kuo-Cheng Lien ,  Chang-Sheng Lin ,  Chih-Chang Hung ,  Yung-Cheng Lu

IPC分类号： H01L21/3105 ,  H01L29/06 ,  H01L21/02 ,  H01L21/311 ,  H01L21/308

CPC分类号： H01L21/31055 ,  H01L21/02282 ,  H01L21/28123 ,  H01L21/3086 ,  H01L21/31058 ,  H01L21/31116 ,  H01L21/31138 ,  H01L21/31144 ,  H01L21/32136 ,  H01L21/823821 ,  H01L21/845 ,  H01L29/0692 ,  H01L29/66545 ,  H01L29/66795

摘要： The present disclosure provides a method of manufacturing an integrated circuit device in some embodiments. In the method, a semiconductor substrate is processed through a series of operations to form a topographically variable surface over the semiconductor substrate. The topographically variable surface varies in height across the semiconductor substrate. A polymeric bottom anti-reflective coating (BARC) is provided over the topographically variable surface. Chemical mechanical polishing is performed to remove a first portion of the BARC, and etching effectuates a top-down recessing of the BARC.

摘要翻译： 本公开提供了在一些实施例中制造集成电路器件的方法。 在该方法中，通过一系列操作来处理半导体衬底，以在半导体衬底上形成拓扑可变表面。 地形可变表面在半导体衬底上的高度变化。 在地形可变表面上提供聚合物底部抗反射涂层（BARC）。 执行化学机械抛光以去除BARC的第一部分，并且蚀刻实现BARC的自上而下的凹陷。

公开(公告)号：US09236446B2

公开(公告)日：2016-01-12

申请号：US14208697

申请日：2014-03-13

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Wen-Kuei Liu ,  Teng-Chun Tsai ,  Kuo-Yin Lin ,  Shen-Nan Lee ,  Yu-Wei Chou ,  Kuo-Cheng Lien ,  Chang-Sheng Lin ,  Chih-Chang Hung ,  Yung-Cheng Lu

IPC分类号： H01L21/302 ,  H01L21/461 ,  H01L29/66 ,  H01L21/3105 ,  H01L21/311 ,  H01L21/02

CPC分类号： H01L21/31055 ,  H01L21/02282 ,  H01L21/28123 ,  H01L21/3086 ,  H01L21/31058 ,  H01L21/31116 ,  H01L21/31138 ,  H01L21/31144 ,  H01L21/32136 ,  H01L21/823821 ,  H01L21/845 ,  H01L29/0692 ,  H01L29/66545 ,  H01L29/66795

摘要： An IC device manufacturing process effectuates a planar recessing of material that initially varies in height across a substrate. The method includes forming a bottom anti-reflective coating (BARC), baking to induce cross-linking in the BARC, CMP to remove a first portion of the BARC and form a planar surface, then plasma etching to effectuate a planar recessing of the BARC. The plasma etching can have a low selectivity between the BARC and the material being recessed, whereby the BARC and the material are recessed simultaneously. Any of the material above a certain height is removed. Structures that are substantially below that certain height can be protected from contamination and left intact. The method can be particularly effective when an abrasive used during CMP forms ester linkages with the BARC.

摘要翻译： IC器件制造工艺实现了最初在衬底上高度变化的材料的平面凹陷。 该方法包括形成底部抗反射涂层（BARC），烘焙以在BARC，CMP中引发交联以除去BARC的第一部分并形成平坦表面，然后进行等离子体蚀刻以实现BARC的平面凹陷 。 等离子体蚀刻可以在BARC和被凹入的材料之间具有低选择性，由此BARC和材料同时凹陷。 任何高于一定高度的材料都被去除。 可以保护基本上低于该特定高度的结构免受污染并保持不变。 当CMP中使用的研磨剂与BARC形成酯键时，该方法可以是特别有效的。

公开(公告)号：US20150235858A1

公开(公告)日：2015-08-20

申请号：US14181814

申请日：2014-02-17

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Shen-Nan Lee ,  Teng-Chun Tsai ,  Hsin-Hsien Lu ,  Chang-Sheng Lin ,  Kuo-Cheng Lien ,  Kuo-Yin Lin ,  Wen-Kuei Liu ,  Yu-Wei Chou

IPC分类号： H01L21/306 ,  H01L21/66 ,  B24B21/00 ,  H01L21/02 ,  B24B9/06 ,  B24B7/22

CPC分类号： H01L21/0209 ,  B24B7/228 ,  B24B9/065 ,  B24B21/002 ,  H01L21/02043 ,  H01L21/02057 ,  H01L21/02087 ,  H01L21/02096 ,  H01L21/30625 ,  H01L21/67092 ,  H01L21/67288 ,  H01L22/12 ,  H01L22/20

摘要： A wafer polishing process includes polishing a central area on the back side of a wafer, polishing a peripheral area on the back side of the wafer, buffing the central area, and buffing the peripheral area. The process can significantly reduce scratch-related wafer breakage, can correct focus spots on wafers, and can replace cleaning processes that use chemical etchants. Polishing and buffing can include polishing and buffing the bevel region. Further improvements include polishing with abrasive pads having a soft backing, polishing or buffing with pads having relatively soft abrasive particles, polishing or buffing with abrasive pads made from abrasive particles that have been sorted and selected for regularity of shape, irrigating the surface being polished or buffed with an aqueous solution that includes a friction-reducing agent, and buffing with abrasive pads having 20k or finer grit or non-abrasive pads.

摘要翻译： 晶片抛光工艺包括抛光晶片背面的中心区域，抛光晶片背面的周边区域，抛光中心区域，以及抛光周边区域。 该过程可以显着减少划痕相关的晶片断裂，可以校正晶片上的焦点，并可以替代使用化学蚀刻剂的清洗工艺。 抛光和抛光可以包括抛光和抛光斜面区域。 进一步的改进包括用具有柔软背衬的研磨垫，抛光或抛光，具有相对较软的磨料颗粒的垫，抛光或抛光，其中由磨料颗粒制成的研磨垫已被分选并选择成规则形状，冲洗正被抛光的表面 用包含减摩剂的水溶液抛光，并用具有20k或更细砂粒或非研磨垫的研磨垫进行抛光。