公开(公告)号：US11694909B2

公开(公告)日：2023-07-04

申请号：US16587788

申请日：2019-09-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chang-Sheng Lin ,  Hsin-Hsien Lu

IPC: H01L21/67 ,  H01L21/02 ,  B24B37/34

CPC classification number: H01L21/67046 ,  B24B37/34 ,  H01L21/0209 ,  H01L21/67051

Abstract: The present disclosure, in some embodiments, relates to a brush cleaning apparatus. The brush cleaning apparatus includes a wafer support configured to support a wafer. The brush cleaning apparatus also includes a cleaning brush including a porous material coupled to a core material. An uppermost surface of the porous material defines a planar cleaning surface. A first nozzle is configured to apply a first cleaning liquid directly between the wafer and the planar cleaning surface of the cleaning brush.

公开(公告)号：US11458587B2

公开(公告)日：2022-10-04

申请号：US16515300

申请日：2019-07-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chang-Sheng Lin ,  Hsin-Hsien Lu

IPC: B24B37/30 ,  B24B37/32 ,  B24B37/04 ,  B24B37/10 ,  B24B37/20

Abstract: Some embodiments relate to a carrier head. The carrier head includes a housing configured to enclose a wafer, wherein the housing includes a retaining ring recess configured to circumferentially surround the wafer. A retaining ring, which includes a first ring-shaped layer and a second ring-shaped layer, is disposed in the retaining ring recess. The second ring-shaped layer is disposed deeper in the retaining ring recess than the first ring-shaped layer and separates the first ring-shaped layer from a bottom of the retaining ring recess. A hardness of the second ring-shaped layer is less than a hardness of the first ring-shaped layer.

公开(公告)号：US11011385B2

公开(公告)日：2021-05-18

申请号：US15686922

申请日：2017-08-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wen-Kuei Liu ,  Teng-Chun Tsai ,  Kuo-Yin Lin ,  Shen-Nan Lee ,  Yu-Wei Chou ,  Kuo-Cheng Lien ,  Chang-Sheng Lin ,  Chih-Chang Hung ,  Yung-Cheng Lu

IPC: H01L21/3105 ,  H01L21/84 ,  H01L21/28 ,  H01L21/3213 ,  H01L21/027 ,  H01L21/311 ,  H01L21/8238 ,  H01L29/66

Abstract: A method of manufacturing an integrated circuit device is provided. A first feature, which has a first susceptibility to damage by chemical mechanical processing (CMP), is formed at a first height as measured from an upper surface of the substrate. A second feature, which has a second susceptibility to damage by the CMP, is formed at a second height as measured from the upper surface of the substrate and is laterally spaced from the first feature by a recess. The second height is greater than the first height, and the second susceptibility is less than the first susceptibility. A sacrificial coating is formed in the recess over an uppermost surface of the first feature. CMP is performed to remove a first portion of the sacrificial coating and expose an upper surface of the second feature while leaving a second portion of the sacrificial coating in place over the first feature.

公开(公告)号：US09852899B2

公开(公告)日：2017-12-26

申请号：US15407893

申请日：2017-01-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shen-Nan Lee ,  Teng-Chun Tsai ,  Hsin-Hsien Lu ,  Chang-Sheng Lin ,  Kuo-Cheng Lien ,  Kuo-Yin Lin ,  Wen-Kuei Liu ,  Yu-Wei Chou

IPC: H01L21/02 ,  H01L21/66 ,  H01L21/67 ,  B24B7/22 ,  B24B9/06

CPC classification number: H01L21/0209 ,  B24B7/228 ,  B24B9/065 ,  B24B21/002 ,  H01L21/02043 ,  H01L21/02057 ,  H01L21/02087 ,  H01L21/02096 ,  H01L21/30625 ,  H01L21/67092 ,  H01L21/67288 ,  H01L22/12 ,  H01L22/20

Abstract: Some embodiments are directed to a wafer polishing tool. The wafer polishing tool includes a first polisher, a second polisher downstream of the first polisher, a third polisher downstream of the second polisher, and a fourth polisher downstream of the third polisher. The first polisher receives a wafer having a front side and a back side with integrated circuit component devices disposed on the front side of the wafer, and polishes a center region on the back side of the wafer. The second polisher receives the wafer via transporting equipment and buffs the center region of the back side of the wafer. The third polisher receives the wafer via the transporting equipment and polishes a back side edge region of the wafer. The fourth polisher receives the wafer via the transporting equipment and buffs the back side edge region of the wafer.

公开(公告)号：US09415479B2

公开(公告)日：2016-08-16

申请号：US13762414

申请日：2013-02-08

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chang-Sheng Lin ,  Hsin-Hsien Lu

IPC: B24B37/24 ,  B24B37/26

CPC classification number: B24B37/24 ,  B24B37/26

Abstract: A polishing pad for polishing a substrate. The pad comprises a layer of material having an upper polishing surface and a lower surface interfacing with a proximate platen, the material comprising a mixture of a conductive polymer distributed in a structure of a dielectric polymeric material using predetermined relationships. Additional embodiments provide a pad having a layer of dielectric polymeric material with an upper polishing surface and a lower surface interfacing with a proximate platen. A first set of grooves filled with a conductive polymer extends from the upper polishing surface to the lower surface, the first set of grooves filled with a conductive polymer. A second set of shallower grooves provide for slurry flow over the upper polishing surface. The first and/or second set of grooves are provided in a predetermined pattern.

Abstract translation: 一种用于抛光衬底的抛光垫。 衬垫包括具有上抛光表面和与邻近压板接合的下表面的材料层，该材料包括使用预定关系分布在电介质聚合物材料的结构中的导电聚合物的混合物。 另外的实施例提供了具有一层电介质聚合材料的焊盘，其具有上抛光表面和与邻近压板相接合的下表面。 填充有导电聚合物的第一组凹槽从上抛光表面延伸到下表面，第一组凹槽填充有导电聚合物。 第二组较浅的槽提供了在上抛光表面上的浆料流动。 以预定图案提供第一组和/或第二组凹槽。

公开(公告)号：US20160172209A1

公开(公告)日：2016-06-16

申请号：US15047793

申请日：2016-02-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wen-Kuei Liu ,  Teng-Chun Tsai ,  Kuo-Yin Lin ,  Shen-Nan Lee ,  Yu-Wei Chou ,  Kuo-Cheng Lien ,  Chang-Sheng Lin ,  Chih-Chang Hung ,  Yung-Cheng Lu

IPC: H01L21/3105 ,  H01L21/3213 ,  H01L21/311 ,  H01L21/027 ,  H01L21/28

CPC classification number: H01L21/31055 ,  H01L21/0273 ,  H01L21/0274 ,  H01L21/28008 ,  H01L21/31058 ,  H01L21/31116 ,  H01L21/31133 ,  H01L21/31138 ,  H01L21/3213 ,  H01L21/32139 ,  H01L21/823821 ,  H01L21/845 ,  H01L29/66545

Abstract: An IC device manufacturing process effectuates a planar recessing of material that initially varies in height across a substrate. The method includes forming a polymer coating, CMP to form a planar surface, then plasma etching to effectuate a planar recessing of the polymer coating. The material can be recessed together with the polymer coating, or subsequently with the recessed polymer coating providing a mask. Any of the material above a certain height is removed. Structures that are substantially below that certain height can be protected from contamination and left intact. The polymer can be a photoresist. The polymer can be provided with suitable adhesion and uniformity for the CMP process through a two-step baking process and by exhausting the baking chamber from below the substrate.

公开(公告)号：US12011803B2

公开(公告)日：2024-06-18

申请号：US16419256

申请日：2019-05-22

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chang-Sheng Lin

IPC: B24B53/017 ,  B24B37/04 ,  B24B37/10 ,  B24B37/30 ,  B24B37/32 ,  B24B53/02 ,  H01L21/306 ,  H01L21/67 ,  B24B37/005

CPC classification number: B24B53/017 ,  B24B37/10 ,  B24B37/30 ,  B24B37/32 ,  B24B53/02 ,  H01L21/30625 ,  H01L21/67253 ,  B24B37/005 ,  B24B37/042

Abstract: The present disclosure, in some embodiments, relates to a polishing system. The polishing system includes a carrier head configured to enclose a wafer. The carrier head has a retainer ring configured to laterally surround the wafer and an abrasive structure that partially covers a lower surface of the retainer ring. A membrane support is surrounded by the retainer ring and defines one or more ports. One or more chambers are coupled to the one or more ports and are defined by the membrane support and a flexible membrane having a lower surface configured to contact the wafer.

公开(公告)号：US10300578B2

公开(公告)日：2019-05-28

申请号：US15436953

申请日：2017-02-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chang-Sheng Lin

IPC: B24B37/10 ,  B24B37/30 ,  B24B37/32 ,  B24B53/02 ,  B24B37/005 ,  B24B53/017 ,  H01L21/306 ,  H01L21/67 ,  B24B37/04

Abstract: In some embodiments, the present disclosure relates to a method of performing a planarization process. The method may be performed by placing a wafer between a carrier head and an upper surface of a polishing pad. The carrier head has a retainer ring configured to surround the wafer, and the retainer ring has an abrasive structure configured to contact the upper surface of the polishing pad. Pressures within one or more chambers surrounded by the carrier head are independently regulated. The one or more chambers have one or more interior surfaces having a flexible membrane. The flexible membrane has a lower surface configured to contact the wafer. At least one of the carrier head or the polishing pad are moved relative to the other, and a roughness of the upper surface of the polishing pad is maintained within a predetermined range by using the abrasive structure of the retainer ring.

公开(公告)号：US09748109B2

公开(公告)日：2017-08-29

申请号：US15047793

申请日：2016-02-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wen-Kuei Liu ,  Teng-Chun Tsai ,  Kuo-Yin Lin ,  Shen-Nan Lee ,  Yu-Wei Chou ,  Kuo-Cheng Lien ,  Chang-Sheng Lin ,  Chih-Chang Hung ,  Yung-Cheng Lu

IPC: H01L21/3105 ,  H01L21/027 ,  H01L21/311 ,  H01L21/28 ,  H01L21/3213 ,  H01L21/8238 ,  H01L21/84 ,  H01L29/66

CPC classification number: H01L21/31055 ,  H01L21/0273 ,  H01L21/0274 ,  H01L21/28008 ,  H01L21/31058 ,  H01L21/31116 ,  H01L21/31133 ,  H01L21/31138 ,  H01L21/3213 ,  H01L21/32139 ,  H01L21/823821 ,  H01L21/845 ,  H01L29/66545

Abstract: An IC device manufacturing process effectuates a planar recessing of material that initially varies in height across a substrate. The method includes forming a polymer coating, CMP to form a planar surface, then plasma etching to effectuate a planar recessing of the polymer coating. The material can be recessed together with the polymer coating, or subsequently with the recessed polymer coating providing a mask. Any of the material above a certain height is removed. Structures that are substantially below that certain height can be protected from contamination and left intact. The polymer can be a photoresist. The polymer can be provided with suitable adhesion and uniformity for the CMP process through a two-step baking process and by exhausting the baking chamber from below the substrate.

公开(公告)号：US20170182628A1

公开(公告)日：2017-06-29

申请号：US15459192

申请日：2017-03-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chang-Sheng Lin ,  Hsin-Hsien Lu

IPC: B24B37/04 ,  B24B37/20 ,  B24B37/32

CPC classification number: B24B37/042 ,  B24B37/105 ,  B24B37/20 ,  B24B37/30 ,  B24B37/32

Abstract: Some embodiments relate to a method of using a polishing system. In this method, a wafer is secured in a carrier head. The carrier head includes a housing, which includes a retaining ring recess, enclosing the wafer. A retaining ring is positioned in the retaining ring recess. The retaining ring surrounds the wafer, and has a hardness ranging from about 5 shore A to about 80 shore D. The wafer is pressed against a polishing pad, and at least one of the carrier head or the polishing pad is moved relative to the other.