Invention Grant
US09563256B2 Processor hiding its power-up latency with activation of a root port and quickly sending a downstream cycle
有权
处理器通过激活根端口隐藏其上电延迟并快速发送下游周期
- Patent Title: Processor hiding its power-up latency with activation of a root port and quickly sending a downstream cycle
- Patent Title (中): 处理器通过激活根端口隐藏其上电延迟并快速发送下游周期
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Application No.: US13734577Application Date: 2013-01-04
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Publication No.: US09563256B2Publication Date: 2017-02-07
- Inventor: Sun Zheng E , Ting Lok Song , Poh Thiam Teoh , Jennifer Chin , Say Cheong Gan , Sujea Lim , Su Wei Lim
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Patent Capital Group
- Main IPC: G06F1/32
- IPC: G06F1/32
Abstract:
Particular embodiments described herein can offer a method that includes powering down a root port; initiating a first downstream cycle by a central processing unit (CPU) to the root port; identifying a power up activity for the CPU; and triggering an exit flow for a power state in conjunction with sending a second downstream cycle to the root port. In more particular embodiments, the triggering of the exit flow for the power state and the sending of the second downstream cycle to the root port occurs in a substantially parallel fashion. In addition, a prewake indicator can be sent to the root port to trigger the exit flow before the CPU is powered up and the second downstream cycle is sent.
Public/Granted literature
- US20140195835A1 SYSTEM AND METHOD FOR PROVIDING POWER SAVINGS IN A PROCESSOR ENVIRONMENT Public/Granted day:2014-07-10
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