公开(公告)号：US10209911B2

公开(公告)日：2019-02-19

申请号：US15024717

申请日：2014-09-16

Applicant: INTEL CORPORATION

Inventor： Jennifer Chin ,  Su Wei Lim ,  Poh Thiam Teoh ,  Ting Lok Song ,  Sun Zheng E ,  Say Cheong Gan

IPC: G06F1/32 ,  G06F3/06

Abstract: Various embodiments are generally directed to an apparatus, method and other techniques for determining when a communications port is in a first low power state, determining that a coupled device entered a low power state and enabling a second low power state based on the determination that the device has entered the low power state, the second low power state to use less power than the first low power state.

公开(公告)号：US09563256B2

公开(公告)日：2017-02-07

申请号：US13734577

申请日：2013-01-04

Applicant: Intel Corporation

Inventor： Sun Zheng E ,  Ting Lok Song ,  Poh Thiam Teoh ,  Jennifer Chin ,  Say Cheong Gan ,  Sujea Lim ,  Su Wei Lim

IPC: G06F1/32

CPC classification number: G06F1/3253 ,  Y02D10/151 ,  Y02D50/20

Abstract: Particular embodiments described herein can offer a method that includes powering down a root port; initiating a first downstream cycle by a central processing unit (CPU) to the root port; identifying a power up activity for the CPU; and triggering an exit flow for a power state in conjunction with sending a second downstream cycle to the root port. In more particular embodiments, the triggering of the exit flow for the power state and the sending of the second downstream cycle to the root port occurs in a substantially parallel fashion. In addition, a prewake indicator can be sent to the root port to trigger the exit flow before the CPU is powered up and the second downstream cycle is sent.

Abstract translation: 本文描述的特定实施例可以提供一种方法，其包括断电根端口; 通过中央处理单元（CPU）向根端口发起第一下游循环; 识别CPU的加电活动; 并且触发用于电力状态的退出流，同时向根端口发送第二下游循环。 在更具体的实施例中，用于功率状态的出口流的触发和将第二下游循环发送到根端口以基本上平行的方式发生。 另外，在CPU上电并发送第二个下游周期之前，可以将根据端口发送预取指示符以触发退出流。

公开(公告)号：US20170083079A1

公开(公告)日：2017-03-23

申请号：US15370507

申请日：2016-12-06

Applicant: Intel Corporation

Inventor： Jennifer Chin ,  Su Wei Lim ,  Poh Thiam Teoh ,  Ting Lok Song ,  Sun Zheng E ,  Say Cheong Gan ,  Sujea Lim ,  Ming Yi Lim

IPC: G06F1/32 ,  G06F13/42

CPC classification number: G06F1/3287 ,  G06F1/1626 ,  G06F1/3206 ,  G06F1/3218 ,  G06F1/3243 ,  G06F13/4282 ,  G06F2213/0026 ,  Y02D10/151 ,  Y02D10/152

Abstract: Particular embodiments described herein can offer a method for managing power for at least one processor that includes evaluating a plurality of ports associated with an electronic device; determining that a particular pin associated with at least one of the ports is not receiving a signal; disabling a squelch function associated with the electronic device; and gating power associated with a physical layer (PHY) of the electronic device.

公开(公告)号：US10248183B2

公开(公告)日：2019-04-02

申请号：US15370507

申请日：2016-12-06

Applicant: Intel Corporation

Inventor： Jennifer Chin ,  Su Wei Lim ,  Poh Thiam Teoh ,  Ting Lok Song ,  Sun Zheng E ,  Say Cheong Gan ,  Sujea Lim ,  Ming Yi Lim

IPC: G06F1/32 ,  G06F1/3287 ,  G06F1/16 ,  G06F1/3206 ,  G06F1/3234 ,  G06F1/3218 ,  G06F13/42

Abstract: Particular embodiments described herein can offer a method for managing power for at least one processor that includes evaluating a plurality of ports associated with an electronic device; determining that a particular pin associated with at least one of the ports is not receiving a signal; disabling a squelch function associated with the electronic device; and gating power associated with a physical layer (PHY) of the electronic device.

公开(公告)号：US09124455B1

公开(公告)日：2015-09-01

申请号：US14495768

申请日：2014-09-24

Applicant: INTEL CORPORATION

Inventor： Su Wei Lim ,  Ronald W. Swartz ,  Yueming Jiang ,  Hooi Kar Loo ,  Athourina Gevergiz ,  Bruce A. Tennant ,  Yick Yaw Ho ,  Poh Thiam Teoh ,  Jennifer Chin ,  Hui Shi

IPC: H03H7/30 ,  H04L25/03

CPC classification number: H04L25/03885 ,  H04L25/03343 ,  H04L2025/03681

Abstract: Techniques for embedded high speed serial interface methods are described herein. The techniques provide an apparatus for link equalization including an equalization control module to determine at least a first coefficient setting and a second coefficient setting at a remote transmitter based on an algorithm. The apparatus also includes a receiver margining module to determine a first margin value to be associated with the first coefficient setting and a second margin value to be associated with the second coefficient setting. The receiver margining module is to further determine if at least the first margin value is higher than the second margin value.

Abstract translation: 本文描述了嵌入式高速串行接口方法的技术。 这些技术提供了一种用于链路均衡的装置，包括均衡控制模块，用于基于算法确定在远程发射机处的至少第一系数设置和第二系数设置。 该装置还包括接收器边界模块，用于确定与第一系数设置相关联的第一边距值和与第二系数设置相关联的第二边距值。 接收器余量模块用于进一步确定至少第一边际值是否高于第二边际值。

公开(公告)号：US09513662B2

公开(公告)日：2016-12-06

申请号：US13734612

申请日：2013-01-04

Applicant: Intel Corporation

Inventor： Jennifer Chin ,  Su Wei Lim ,  Poh Thiam Teoh ,  Ting Lok Song ,  Sun Zheng E ,  Say Cheong Gan ,  Sujea Lim ,  Ming Yi Lim

IPC: G06F1/00 ,  G06F1/16 ,  G06F1/32

CPC classification number: G06F1/3287 ,  G06F1/1626 ,  G06F1/3206 ,  G06F1/3218 ,  G06F1/3243 ,  G06F13/4282 ,  G06F2213/0026 ,  Y02D10/151 ,  Y02D10/152

Abstract: Particular embodiments described herein can offer a method for managing power for at least one processor that includes evaluating a plurality of ports associated with an electronic device; determining that a particular pin associated with at least one of the ports is not receiving a signal; disabling a squelch function associated with the electronic device; and gating power associated with a physical layer (PHY) of the electronic device.

Abstract translation: 本文描述的特定实施例可以提供一种用于管理至少一个处理器的功率的方法，该处理器包括评估与电子设备相关联的多个端口; 确定与所述端口中的至少一个相关联的特定引脚没有接收到信号; 禁用与所述电子设备相关联的静噪功能; 以及与电子设备的物理层（PHY）相关联的门控功率。