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US09563597B2 High capacity memory systems with inter-rank skew tolerance 有权
具有跨级偏差容限的高容量存储器系统

High capacity memory systems with inter-rank skew tolerance
Abstract:
In a multirank memory system in which the clock distribution trees of each rank are permitted to drift over a wide range (e.g., low power memory systems), the fine-interleaving of commands between ranks is facilitated through the use of techniques that cause each addressed rank to properly sample commands intended for that rank, notwithstanding the drift. The ability to perform such “microthreading” provides for substantially enhanced memory capacity without sacrificing the performance of single rank systems. This disclosure provides methods, memory controllers, memory devices and system designs adapted to these ends.
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