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公开(公告)号：US11621030B2
公开(公告)日：2023-04-04
申请号：US17568656
申请日：2022-01-04
Applicant: Rambus Inc.
Inventor： Wayne F. Ellis , Wayne S. Richardson , Akash Bansal , Frederick A. Ware , Lawrence Lai , Kishore Ven Kasamsetty
IPC: G11C11/34 , G11C11/406 , G11C7/02 , G11C7/20 , G11C11/4072 , G11C29/02 , G06F1/3234 , G11C11/4074
Abstract: In one embodiment, a memory device includes a memory core and input receivers to receive commands and data. The memory device also includes a register to store a value that indicates whether a subset of the input receivers are powered down in response to a control signal. A memory controller transmits commands and data to the memory device. The memory controller also transmits the value to indicate whether a subset of the input receivers of the memory device are powered down in response to the control signal. In addition, in response to a self-fresh command, the memory device defers entry into a self-refresh operation until receipt of the control signal that is received after receiving the self-refresh command.
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公开(公告)号：US20200294577A1
公开(公告)日：2020-09-17
申请号：US16825247
申请日：2020-03-20
Applicant: Rambus Inc.
Inventor： Wayne F. Ellis , Wayne S. Richardson , Akash Bansal , Frederick A. Ware , Lawrence Lai , Kishore Ven Kasamsetty
IPC: G11C11/406 , G11C7/02 , G11C7/20 , G11C11/4072 , G11C29/02 , G06F1/3234 , G11C11/4074
Abstract: In one embodiment, a memory device includes a memory core and input receivers to receive commands and data. The memory device also includes a register to store a value that indicates whether a subset of the input receivers are powered down in response to a control signal. A memory controller transmits commands and data to the memory device. The memory controller also transmits the value to indicate whether a subset of the input receivers of the memory device are powered down in response to the control signal. In addition, in response to a self-fresh command, the memory device defers entry into a self-refresh operation until receipt of the control signal that is received after receiving the self-refresh command.
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公开(公告)号：US09886993B2
公开(公告)日：2018-02-06
申请号：US15332785
申请日：2016-10-24
Applicant: Rambus Inc.
Inventor： Wayne F. Ellis , Wayne S. Richardson , Akash Bansal , Frederick A. Ware , Lawrence Lai , Kishore Ven Kasamsetty
IPC: G11C5/14 , G11C11/406 , G11C11/4074
CPC classification number: G11C11/40615 , G06F1/3234 , G11C7/02 , G11C7/20 , G11C11/4072 , G11C11/4074 , G11C29/022 , G11C29/028
Abstract: In one embodiment, a memory device includes a memory core and input receivers to receive commands and data. The memory device also includes a register to store a value that indicates whether a subset of the input receivers are powered down in response to a control signal. A memory controller transmits commands and data to the memory device. The memory controller also transmits the value to indicate whether a subset of the input receivers of the memory device are powered down in response to the control signal. In addition, in response to a self-fresh command, the memory device defers entry into a self-refresh operation until receipt of the control signal that is received after receiving the self-refresh command.
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公开(公告)号：US09818463B2
公开(公告)日：2017-11-14
申请号：US15390681
申请日：2016-12-26
Applicant: Rambus Inc.
Inventor： Frederick A. Ware , Ely K. Tsern , Brian S. Leibowitz , Wayne Frederick Ellis , Akash Bansal , John Welsford Brooks , Kishore Ven Kasamsetty
CPC classification number: G11C8/18 , G06F13/161 , G06F13/1647 , G06F13/1657 , G06F13/4234 , G11C5/02 , G11C5/04 , G11C7/10 , G11C7/1072 , G11C29/023 , G11C29/028 , G11C2207/2254
Abstract: In a multirank memory system in which the clock distribution trees of each rank are permitted to drift over a wide range (e.g., low power memory systems), the fine-interleaving of commands between ranks is facilitated through the use of techniques that cause each addressed rank to properly sample commands intended for that rank, notwithstanding the drift. The ability to perform such “microthreading” provides for substantially enhanced memory capacity without sacrificing the performance of single rank systems. This disclosure provides methods, memory controllers, memory devices and system designs adapted to these ends.
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公开(公告)号：US20230282266A1
公开(公告)日：2023-09-07
申请号：US18181185
申请日：2023-03-09
Applicant: Rambus Inc.
Inventor： Wayne F. Ellis , Wayne S. Richardson , Akash Bansal , Frederick A. Ware , Lawrence Lai , Kishore Ven Kasamsetty
IPC: G11C11/406 , G11C7/02 , G11C7/20 , G11C11/4072 , G11C29/02 , G06F1/3234 , G11C11/4074
CPC classification number: G11C11/40615 , G11C7/02 , G11C7/20 , G11C11/4072 , G11C29/022 , G11C29/028 , G06F1/3234 , G11C11/4074
Abstract: In one embodiment, a memory device includes a memory core and input receivers to receive commands and data. The memory device also includes a register to store a value that indicates whether a subset of the input receivers are powered down in response to a control signal. A memory controller transmits commands and data to the memory device. The memory controller also transmits the value to indicate whether a subset of the input receivers of the memory device are powered down in response to the control signal. In addition, in response to a self-fresh command, the memory device defers entry into a self-refresh operation until receipt of the control signal that is received after receiving the self-refresh command.
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Patent Agency Ranking
公开(公告)号：US20170103802A1
公开(公告)日：2017-04-13
申请号：US15332785
申请日：2016-10-24
Applicant: Rambus Inc.
Inventor： Wayne F. Ellis , Wayne S. Richardson , Akash Bansal , Frederick A. Ware , Lawrence Lai , Kishore Ven Kasamsetty
IPC: G11C11/406 , G11C11/4074
CPC classification number: G11C11/40615 , G06F1/3234 , G11C7/02 , G11C7/20 , G11C11/4072 , G11C11/4074 , G11C29/022 , G11C29/028
Abstract: In one embodiment, a memory device includes a memory core and input receivers to receive commands and data. The memory device also includes a register to store a value that indicates whether a subset of the input receivers are powered down in response to a control signal. A memory controller transmits commands and data to the memory device. The memory controller also transmits the value to indicate whether a subset of the input receivers of the memory device are powered down in response to the control signal. In addition, in response to a self-fresh command, the memory device defers entry into a self-refresh operation until receipt of the control signal that is received after receiving the self-refresh command.
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公开(公告)号：US09563597B2
公开(公告)日：2017-02-07
申请号：US14386561
申请日：2012-12-20
Applicant: Rambus Inc.
Inventor： Frederick A. Ware , Ely K. Tsern , Brian S. Leibowitz , Wayne Frederick Ellis , Akash Bansal , John Welsford Brooks , Kishore Ven Kasamsetty
CPC classification number: G11C8/18 , G06F13/161 , G06F13/1647 , G06F13/1657 , G06F13/4234 , G11C5/02 , G11C5/04 , G11C7/10 , G11C7/1072 , G11C29/023 , G11C29/028 , G11C2207/2254
Abstract: In a multirank memory system in which the clock distribution trees of each rank are permitted to drift over a wide range (e.g., low power memory systems), the fine-interleaving of commands between ranks is facilitated through the use of techniques that cause each addressed rank to properly sample commands intended for that rank, notwithstanding the drift. The ability to perform such “microthreading” provides for substantially enhanced memory capacity without sacrificing the performance of single rank systems. This disclosure provides methods, memory controllers, memory devices and system designs adapted to these ends.
Abstract translation: 在允许每个等级的时钟分配树被允许在宽范围内漂移的多存储器存储器系统（例如，低功率存储器系统）中，通过使用引起每个寻址的技术来促进等级之间的命令的精细交错 排名适当地采样旨在该等级的命令，尽管有漂移。 执行这种“微线程”的能力提供了显着增强的存储器容量，而不牺牲单级系统的性能。 本公开提供了适于这些目的的方法，存储器控制器，存储器件和系统设计。
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公开(公告)号：US09502096B2
公开(公告)日：2016-11-22
申请号：US14573323
申请日：2014-12-17
Applicant: Rambus Inc.
Inventor： Wayne F. Ellis , Wayne S. Richardson , Akash Bansal , Frederick A. Ware , Lawrence Lai , Kishore Ven Kasamsetty
IPC: G11C7/00 , G11C11/406 , G11C7/02 , G11C7/20 , G11C11/4072 , G11C29/02 , G06F1/32 , G11C11/4074
CPC classification number: G11C11/40615 , G06F1/3234 , G11C7/02 , G11C7/20 , G11C11/4072 , G11C11/4074 , G11C29/022 , G11C29/028
Abstract: In one embodiment, a memory device includes a memory core and input receivers to receive commands and data. The memory device also includes a register to store a value that indicates whether a subset of the input receivers are powered down in response to a control signal. A memory controller transmits commands and data to the memory device. The memory controller also transmits the value to indicate whether a subset of the input receivers of the memory device are powered down in response to the control signal. In addition, in response to a self-fresh command, the memory device defers entry into a self-refresh operation until receipt of the control signal that is received after receiving the self-refresh command.
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公开(公告)号：US20190180813A1
公开(公告)日：2019-06-13
申请号：US16276338
申请日：2019-02-14
Applicant: Rambus Inc.
Inventor： Wayne F. Ellis , Wayne S. Richardson , Akash Bansal , Frederick A. Ware , Lawrence Lai , Kishore Ven Kasamsetty
IPC: G11C11/406 , G11C11/4074 , G06F1/3234 , G11C29/02 , G11C7/02 , G11C11/4072 , G11C7/20
Abstract: In one embodiment, a memory device includes a memory core and input receivers to receive commands and data. The memory device also includes a register to store a value that indicates whether a subset of the input receivers are powered down in response to a control signal. A memory controller transmits commands and data to the memory device. The memory controller also transmits the value to indicate whether a subset of the input receivers of the memory device are powered down in response to the control signal. In addition, in response to a self-fresh command, the memory device defers entry into a self-refresh operation until receipt of the control signal that is received after receiving the self-refresh command.
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公开(公告)号：US20190139598A1
公开(公告)日：2019-05-09
申请号：US16235351
申请日：2018-12-28
Applicant: Rambus Inc.
Inventor： Wayne F. Ellis , Wayne S. Richardson , Akash Bansal , Frederick A. Ware , Lawrence Lai , Kishore Ven Kasamsetty
IPC: G11C11/406 , G11C11/4074 , G06F1/3234 , G11C29/02 , G11C7/02 , G11C11/4072 , G11C7/20
Abstract: In one embodiment, a memory device includes a memory core and input receivers to receive commands and data. The memory device also includes a register to store a value that indicates whether a subset of the input receivers are powered down in response to a control signal. A memory controller transmits commands and data to the memory device. The memory controller also transmits the value to indicate whether a subset of the input receivers of the memory device are powered down in response to the control signal. In addition, in response to a self-fresh command, the memory device defers entry into a self-refresh operation until receipt of the control signal that is received after receiving the self-refresh command.
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