Invention Grant
- Patent Title: Methodology of grading reliability and performance of chips across wafer
- Patent Title (中): 晶片上芯片的可靠性和性能分级方法
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Application No.: US13649699Application Date: 2012-10-11
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Publication No.: US09575115B2Publication Date: 2017-02-21
- Inventor: Nathaniel R. Chadwick , James P. Di Sarro , Robert J. Gauthier, Jr. , Tom C. Lee , Junjun Li , Souvick Mitra , Kirk D. Peterson , Andrew A. Turner
- Applicant: GLOBALFOUNDRIES INC.
- Applicant Address: KY Grand Cayman
- Assignee: GLOBALFOUNDRIES INC.
- Current Assignee: GLOBALFOUNDRIES INC.
- Current Assignee Address: KY Grand Cayman
- Agency: Gibb & Riley, LLC
- Agent Michael J. LeStrange, Esq.
- Main IPC: G01R31/28
- IPC: G01R31/28 ; H01L21/66

Abstract:
A system and method sorts integrated circuit devices. Integrated circuit devices are manufactured on a wafer according to an integrated circuit design using manufacturing equipment. The design produces integrated circuit devices that are identically designed and perform differently based on manufacturing process variations. The integrated circuit devices are for use in a range of environmental conditions, when placed in service. Testing is performed on the integrated circuit devices. Environmental maximums are individually predicted for each device. The environmental maximums comprise ones of the environmental conditions that must not be exceeded for each device to perform above a given failure rate. Each integrated circuit device is assigned at least one of a plurality of grades based on the environmental maximums predicted for each device. The integrated circuit devices are provided to different forms of service having different ones of the environmental conditions based on the grades assigned to each device.
Public/Granted literature
- US20140107822A1 METHODOLOGY OF GRADING RELIABILITY AND PERFORMANCE OF CHIPS ACROSS WAFER Public/Granted day:2014-04-17
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