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    Methodology of grading reliability and performance of chips across wafer
    2.
    发明授权
    Methodology of grading reliability and performance of chips across wafer 有权
    晶片上芯片的可靠性和性能分级方法

    公开(公告)号：US09575115B2

    公开(公告)日：2017-02-21

    申请号：US13649699

    申请日：2012-10-11

    Applicant: GLOBALFOUNDRIES INC.

    Inventor： Nathaniel R. Chadwick ,  James P. Di Sarro ,  Robert J. Gauthier, Jr. ,  Tom C. Lee ,  Junjun Li ,  Souvick Mitra ,  Kirk D. Peterson ,  Andrew A. Turner

    IPC: G01R31/28 ,  H01L21/66

    CPC classification number: G01R31/2872 ,  G01R31/2831 ,  G01R31/2894 ,  H01L22/14 ,  H01L22/20

    Abstract: A system and method sorts integrated circuit devices. Integrated circuit devices are manufactured on a wafer according to an integrated circuit design using manufacturing equipment. The design produces integrated circuit devices that are identically designed and perform differently based on manufacturing process variations. The integrated circuit devices are for use in a range of environmental conditions, when placed in service. Testing is performed on the integrated circuit devices. Environmental maximums are individually predicted for each device. The environmental maximums comprise ones of the environmental conditions that must not be exceeded for each device to perform above a given failure rate. Each integrated circuit device is assigned at least one of a plurality of grades based on the environmental maximums predicted for each device. The integrated circuit devices are provided to different forms of service having different ones of the environmental conditions based on the grades assigned to each device.

    Abstract translation: 一种系统和方法对集成电路器件进行排序。 根据使用制造设备的集成电路设计，在晶片上制造集成电路器件。 该设计生产的集成电路器件根据制造工艺变化相同设计和执行不同。 集成电路设备在使用时可用于一系列环境条件。 在集成电路器件上进行测试。 每个设备单独预测环境最大值。 环境最大值包括每个设备在给定故障率以上执行时不得超过的环境条件。 基于为每个设备预测的环境最大值，为每个集成电路设备分配多个等级中的至少一个。 基于分配给每个设备的等级，将集成电路设备提供给具有不同环境条件的不同服务形式。

    Self-healing electrostatic discharge power clamp
    3.
    发明授权
    Self-healing electrostatic discharge power clamp 有权
    自愈式静电放电电源钳

    公开(公告)号：US09425185B2

    公开(公告)日：2016-08-23

    申请号：US14290141

    申请日：2014-05-29

    Applicant: GLOBALFOUNDRIES INC.

    Inventor： Robert J. Gauthier, Jr. ,  Tom C. Lee ,  Junjun Li ,  You Li ,  Souvick Mitra

    IPC: H02H9/00 ,  H01L27/02 ,  H01L23/525 ,  H01G17/00 ,  H01G13/00

    CPC classification number: H01L27/0266 ,  H01G13/00 ,  H01G17/00 ,  H01L23/5256 ,  H01L27/0285 ,  H01L2924/0002 ,  Y10T29/435 ,  H01L2924/00

    Abstract: Circuits and methods of fabricating circuits that provide electrostatic discharge protection, as well as methods of protecting an integrated circuit from electrostatic discharge. The protection circuit may include a power clamp device, a timing circuit including a resistor and a capacitor that is coupled with the resistor at a node, and a power clamp device coupled with the timing circuit at the node. The capacitor includes a plurality of capacitor elements. The protection circuit further includes a plurality of electronic fuses. Each electronic fuse is coupled with a respective one of the capacitor elements. A field effect transistor may be coupled in parallel with the resistor of the timing circuit, and may be used to bypass the resistor to provide a programming current to any electronic fuse coupled with a capacitor element of abnormally low impedance.

    Abstract translation: 制造提供静电放电保护的电路的电路和方法，以及保护集成电路免受静电放电的方法。 保护电路可以包括功率钳位装置，包括电阻器的定时电路和与节点处的电阻器耦合的电容器，以及与节点处的定时电路耦合的功率钳位装置。 电容器包括多个电容器元件。 保护电路还包括多个电子保险丝。 每个电子熔断器与相应的一个电容器元件耦合。 场效应晶体管可以与定时电路的电阻并联耦合，并且可以用于旁路电阻器以向与异常低阻抗的电容器元件耦合的任何电子熔丝提供编程电流。

    Vertical fin-type devices and methods
    4.
    发明授权
    Vertical fin-type devices and methods 有权

    公开(公告)号：US10361293B1

    公开(公告)日：2019-07-23

    申请号：US15878478

    申请日：2018-01-24

    Applicant: GLOBALFOUNDRIES INC.

    Inventor： Tsung-Che Tsai ,  Alain F. Loiseau ,  Robert J. Gauthier, Jr. ,  Souvick Mitra ,  You Li ,  Mickey H. Yu

    IPC: H01L29/74 ,  H01L29/868 ,  H01L23/535 ,  H01L21/761 ,  H01L29/66 ,  H01L21/768 ,  H01L29/06 ,  H01L27/02

    Abstract: Disclosed is an integrated circuit (IC) structure that incorporates a string of vertical devices. Embodiments of the IC structure include a string of two or more vertical diodes. Other embodiments include a vertical diode/silicon-controlled rectifier (SCR) string and, more particularly, a diode-triggered silicon-controlled rectifier (VDTSCR). In any case, each embodiment of the IC structure includes an N-well in a substrate and, within that N-well, a P-doped region and an N-doped region that abuts the P-doped region. The P-doped region can be anode of a vertical diode and can be electrically connected to the N-doped region (e.g., by a local interconnect or by contacts and metal wiring) such that the vertical diode is electrically connected to another vertical device (e.g., another vertical diode or a SCR with vertically-oriented features). Also disclosed is a manufacturing method that can be integrated with methods of manufacturing vertical field effect transistors (VFETs).

    Electrostatic discharge protection circuit with a fail-safe mechanism
    8.
    发明授权
    Electrostatic discharge protection circuit with a fail-safe mechanism 有权
    具有故障安全机构的静电放电保护电路

    公开(公告)号：US09413169B2

    公开(公告)日：2016-08-09

    申请号：US14243295

    申请日：2014-04-02

    Applicant: GLOBALFOUNDRIES INC.

    Inventor： James P. Di Sarro ,  Robert J. Gauthier, Jr. ,  Tom C. Lee ,  Junjun Li ,  Souvick Mitra ,  Christopher S. Putnam

    IPC: H02H9/04

    CPC classification number: H02H9/046 ,  H02H9/042

    Abstract: Circuits and methods for providing electrostatic discharge protection. The protection circuit may include a power clamp device, a timing circuit including a resistor and a capacitor that is coupled with the resistor at a node, a transmission gate configured to selectively connect the node of the timing circuit with the power clamp device, and a control circuit coupled with the node. The control circuit is configured to control the transmission gate based upon whether or not the capacitor is defective. The timing circuit may be deactivated if the capacitor in the timing circuit is defective and the associated chip is powered. Alternatively, the timing circuit may be activated if the capacitor in the timing circuit is not defective.

    Abstract translation: 提供静电放电保护的电路和方法。 保护电路可以包括功率钳位装置，包括电阻器的定时电路和与节点处的电阻器耦合的电容器，被配置为选择性地将定时电路的节点与电源钳位装置连接的传输门，以及 控制电路与节点耦合。 控制电路被配置为基于电容器是否有缺陷来控制传输门。 如果定时电路中的电容器有故障并且相关的芯片被供电，则定时电路可以被去激活。 或者，如果定时电路中的电容器没有故障，则定时电路可以被激活。

    Silicon-controlled rectifiers with wells laterally isolated by trench isolation regions
    9.
    发明授权
    Silicon-controlled rectifiers with wells laterally isolated by trench isolation regions 有权

    公开(公告)号：US10692852B2

    公开(公告)日：2020-06-23

    申请号：US16171760

    申请日：2018-10-26

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Alain Loiseau ,  You Li ,  Mickey Yu ,  Tsung-Che Tsai ,  Souvick Mitra ,  Robert J. Gauthier, Jr.

    IPC: H01L29/74 ,  H01L27/02 ,  H01L21/762 ,  H01L29/06 ,  H01L29/66

    Abstract: Silicon-controlled rectifiers and methods for forming a silicon-controlled rectifier. A first well of a first conductivity type is arranged in a substrate, and second and third wells of a second conductivity type are arranged in the substrate between the first well and the top surface of the substrate. A deep trench isolation region is laterally arranged between the first well of the second conductivity type and the second well of the second conductivity type. The second well is adjoined with the first well along a first interface, the third well is adjoined with the first well along a second interface, and the deep trench isolation region extends the top surface of the substrate past the first interface and the second interface and into the first well. A doped region of the first conductivity type is arranged in the substrate between the second well and the top surface of the substrate.

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