Invention Grant
- Patent Title: Cleaning high aspect ratio vias
- Patent Title (中): 清洁高宽比通孔
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Application No.: US14695392Application Date: 2015-04-24
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Publication No.: US09576788B2Publication Date: 2017-02-21
- Inventor: Jie Liu , Seung Park , Anchuan Wang , Zhenjiang Cui , Nitin K. Ingle
- Applicant: Applied Materials, Inc.
- Applicant Address: US CA Santa Clara
- Assignee: Applied Materials, Inc.
- Current Assignee: Applied Materials, Inc.
- Current Assignee Address: US CA Santa Clara
- Agency: Kilpatrick Townsend & Stockton LLP
- Main IPC: H01L21/02
- IPC: H01L21/02 ; H01L21/311 ; H01L27/115 ; H01L21/027 ; H01L21/3065 ; H01L21/308

Abstract:
A method of removing an amorphous silicon/silicon oxide film stack from vias is described. The method may involve a remote plasma comprising fluorine and a local plasma comprising fluorine and a nitrogen-and-hydrogen-containing precursor unexcited in the remote plasma to remove the silicon oxide. The method may then involve a local plasma of inert species to potentially remove any thin carbon layer (leftover from the photoresist) and to treat the amorphous silicon layer in preparation for removal. The method may then involve removal of the treated amorphous silicon layer with several options possibly within the same substrate processing region. The bottom of the vias may then possess exposed single crystal silicon which is conducive to epitaxial single crystal silicon film growth. The methods presented herein may be particularly well suited for 3d NAND (e.g. VNAND) device formation.
Public/Granted literature
- US20160314961A1 CLEANING HIGH ASPECT RATIO VIAS Public/Granted day:2016-10-27
Information query
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