This description relates to a gate electrode of a field effect transistor. An exemplary structure for a field effect transistor includes a substrate; a gate electrode over the substrate including a first top surface and a sidewall; a source/drain (S/D) region at least partially disposed in the substrate on one side of the gate electrode; a spacer on the sidewall distributed between the gate electrode and the S/D region; and a contact etch stop layer (CESL) adjacent to the spacer and further comprising a portion extending over the S/D region, wherein the portion has a second top surface substantially coplanar with the first top surface.