发明授权
- 专利标题： Device having multiple-layer pins in memory MUX1 layout
- 专利标题（中）： 在存储器MUX1布局中具有多层引脚的器件
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申请号： US14835788申请日： 2015-08-26
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公开(公告)号： US09589885B2公开(公告)日： 2017-03-07
- 发明人: Hung-Jen Liao , Jung-Hsuan Chen , Chien Chi Tien , Ching-Wei Wu , Jui-Che Tsai , Hong-Chen Cheng , Chung-Hsing Wang
- 申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
- 申请人地址： TW
- 专利权人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
- 当前专利权人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
- 当前专利权人地址： TW
- 代理机构： Hauptman Ham, LLP
- 主分类号： H01L23/00
- IPC分类号： H01L23/00 ; H01L23/50 ; H01L27/11 ; H01L23/532 ; H01L27/02 ; H01L23/528 ; H01L23/498 ; H01L23/522
摘要：
An integrated circuit (IC) memory device includes a first conductive layer. The IC memory device also includes a second conductive layer over the first conductive layer. The IC memory device further includes a first-type pin box electrically coupled with the first conductive layer. The IC memory device additionally includes a second-type pin box, different from the first-type pin box, electrically coupled with the second conductive layer.
公开/授权文献
- US20150364412A1 DEVICE HAVING MULTIPLE-LAYER PINS IN MEMORY MUX1 LAYOUT 公开/授权日：2015-12-17
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