公开(公告)号：US12190986B2

公开(公告)日：2025-01-07

申请号：US18447904

申请日：2023-08-10

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Ku-Feng Lin ,  Jui-Che Tsai ,  Perng-Fei Yuh ,  Yih Wang

IPC: G11C7/06 ,  H01L27/06 ,  H03K3/037 ,  H03K3/356

Abstract: A sense amplifier including a first input transistor having a first input gate and a first drain/source terminal, a second input transistor having a second input gate and a second drain/source terminal, a latch circuit, and a first capacitor. The latch circuit includes a first latch transistor having a third drain/source terminal connected to the first drain/source terminal and a second latch transistor having a fourth drain/source terminal connected to the second drain/source terminal. The first capacitor is connected on one side to the first input gate and on another side to the fourth drain/source terminal to reduce a coupling effect in the sense amplifier.

公开(公告)号：US12190945B2

公开(公告)日：2025-01-07

申请号：US18298045

申请日：2023-04-10

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Jui-Che Tsai ,  Chen-Lin Yang ,  Yu-Hao Hsu ,  Shih-Lien Linus Lu

IPC: G11C11/418 ,  G06F7/58 ,  G11C5/14 ,  G11C7/12 ,  G11C8/08

Abstract: A memory device includes a memory cell array including a plurality of bit cells, each of the bit cells coupled to one of a plurality of bit lines and one of a plurality of word lines, respectively, wherein each of the plurality of bit cells is configured to: present an initial logic state during a random number generator (RNG) phase; and operate as a memory cell at a first voltage level during a SRAM phase; and a controller controlling bit line signals on the plurality of bit lines and word line signals on the plurality of word lines, wherein the controller is configured to: during the RNG phase, precharge the plurality of bit lines to a second voltage level, and determine the initial logic states of the plurality of bit cells to generate at least one random number, wherein the second voltage level is lower than the first voltage level.

公开(公告)号：US20240295603A1

公开(公告)日：2024-09-05

申请号：US18350512

申请日：2023-07-11

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chia-En Huang ,  Jui-Che Tsai ,  Ku-Feng Lin ,  Yih Wang

IPC: G01R31/3177 ,  G01R31/317 ,  G01R31/3185 ,  H03K19/173

CPC classification number: G01R31/3177 ,  G01R31/31725 ,  G01R31/318533 ,  H03K19/1737

Abstract: A circuit includes a plurality of first inputs corresponding to a first I/O of an I/O circuit and configured to receive at least a first input signal or a second input signal; a multiplexer compressor coupled to the plurality of first inputs, and configured to alternately form a first testing path for the first input signal and a second testing path for the second input signal; a first output configured to provide a first output signal, through one of the first testing path or the second testing path, as a shifted version of a third input signal; and a second output configured to provide a second output signal, through one of the first testing path or the second testing path, as a captured version of the first input signal or the second input signal.

公开(公告)号：US20230298665A1

公开(公告)日：2023-09-21

申请号：US18300706

申请日：2023-04-14

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Perng-Fei Yuh ,  Yih Wang ,  Ku-Feng Lin ,  Jui-Che Tsai ,  Hiroki Noguchi ,  Fu-An Wu

IPC: G11C14/00 ,  G11C11/419 ,  G11C11/16

CPC classification number: G11C14/0081 ,  G11C11/161 ,  G11C11/1659 ,  G11C11/1675 ,  G11C11/419

Abstract: Disclosed herein is an integrated circuit including multiple magnetic tunneling junction (MTJ) cells coupled to a static random access memory (SRAM). In one aspect, the integrated circuit includes a SRAM having a first port and a second port, and a set of pass transistors coupled to the first port of the SRAM. In one aspect, the integrated circuit includes a set of MTJ cells, where each of the set of MTJ cells is coupled between a select line and a corresponding one of the set of pass transistors.

公开(公告)号：US11657873B2

公开(公告)日：2023-05-23

申请号：US17409341

申请日：2021-08-23

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Perng-Fei Yuh ,  Yih Wang ,  Ku-Feng Lin ,  Jui-Che Tsai ,  Hiroki Noguchi ,  Fu-An Wu

IPC: G11C14/00 ,  G11C11/419 ,  G11C11/16

CPC classification number: G11C14/0081 ,  G11C11/161 ,  G11C11/1659 ,  G11C11/1675 ,  G11C11/419

Abstract: Disclosed herein is an integrated circuit including multiple magnetic tunneling junction (MTJ) cells coupled to a static random access memory (SRAM). In one aspect, the integrated circuit includes a SRAM having a first port and a second port, and a set of pass transistors coupled to the first port of the SRAM. In one aspect, the integrated circuit includes a set of MTJ cells, where each of the set of MTJ cells is coupled between a select line and a corresponding one of the set of pass transistors.

公开(公告)号：US20230057357A1

公开(公告)日：2023-02-23

申请号：US17407451

申请日：2021-08-20

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Ku-Feng Lin ,  Jui-Che Tsai ,  Perng-Fei Yuh ,  Yih Wang

IPC: G11C11/16 ,  H03K3/037 ,  H01L27/06

Abstract: A sense amplifier including a first input transistor having a first input gate and a first drain/source terminal, a second input transistor having a second input gate and a second drain/source terminal, a latch circuit, and a first capacitor. The latch circuit includes a first latch transistor having a third drain/source terminal connected to the first drain/source terminal and a second latch transistor having a fourth drain/source terminal connected to the second drain/source terminal. The first capacitor is connected on one side to the first input gate and on another side to the fourth drain/source terminal to reduce a coupling effect in the sense amplifier.

公开(公告)号：US11189342B2

公开(公告)日：2021-11-30

申请号：US17010483

申请日：2020-09-02

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Pankaj Aggarwal ,  Jui-Che Tsai ,  Ching-Wei Wu

IPC: G11C11/419 ,  G11C11/418 ,  G11C7/10 ,  G11C7/18

Abstract: A method of operating a memory macro includes receiving a first signal indicating a first operational mode of the memory macro, receiving a second signal indicating a second operational mode of the memory macro, generating, by a first logic circuit, a third signal and a fourth signal based on the first signal and a fifth signal thereby causing a change in the first operational mode of the memory macro, and generating, by a second logic circuit, the fifth signal and a sixth signal based on at least the second signal and thereby causing a change in the second operational mode of the memory macro. The first logic circuit is coupled to a first memory cell array and a first IO circuit. The second logic circuit is coupled to a first and second set of word line driver circuits.

公开(公告)号：US20240305481A1

公开(公告)日：2024-09-12

申请号：US18670367

申请日：2024-05-21

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Shih-Lien Linus Lu ,  Jui-Che Tsai ,  Cheng-En Lee

IPC: H04L9/32 ,  H01L21/8238 ,  H03K19/096 ,  H04L9/08

CPC classification number: H04L9/3278 ,  H01L21/823807 ,  H03K19/0963 ,  H04L9/0866 ,  H04L2209/12

Abstract: A PUF generator includes a difference generator circuit with first and second transistors having a first predetermined VT. The difference generator circuit is configured to provide a first output signal for generating a PUF signature based on respective turn on times of the first and second transistors. An amplifier includes a plurality of transistors having a second predetermined VT. The amplifier is configured to receive the first output signal and output the PUF signature.

公开(公告)号：US11903188B2

公开(公告)日：2024-02-13

申请号：US17673126

申请日：2022-02-16

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： Perng-Fei Yuh ,  Yih Wang ,  Meng-Sheng Chang ,  Jui-Che Tsai ,  Ku-Feng Lin ,  Yu-Wei Lin ,  Keh-Jeng Chang ,  Chansyun David Yang ,  Shao-Ting Wu ,  Shao-Yu Chou ,  Philex Ming-Yan Fan ,  Yoshitaka Yamauchi ,  Tzu-Hsien Yang

IPC: G11C17/16 ,  H10B20/20 ,  G11C17/18

CPC classification number: H10B20/20 ,  G11C17/16 ,  G11C17/18

Abstract: The present disclosure provides a memory device, a semiconductor device, and a method of operating a memory device. A memory device includes a memory cell, a bit line, a word line, a select transistor, a fuse element, and a heater. The bit line is connected to the memory cell. The word line is connected to the memory cell. The select transistor is disposed in the memory cell. A gate of the select transistor is connected to the word line. The fuse element is disposed in the memory cell. The fuse element is connected to the bit line and the select transistor. The heater is configured to heat the fuse element.

公开(公告)号：US20230245696A1

公开(公告)日：2023-08-03

申请号：US18298045

申请日：2023-04-10

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Jui-Che Tsai ,  Chen-Lin Yang ,  Yu-Hao Hsu ,  Shih-Lien Linus Lu

IPC: G11C11/418 ,  G11C7/12 ,  G06F7/58 ,  G11C5/14 ,  G11C8/08

CPC classification number: G11C11/418 ,  G06F7/588 ,  G11C5/147 ,  G11C7/12 ,  G11C8/08

Abstract: A memory device includes a memory cell array including a plurality of bit cells, each of the bit cells coupled to one of a plurality of bit lines and one of a plurality of word lines, respectively, wherein each of the plurality of bit cells is configured to: present an initial logic state during a random number generator (RNG) phase; and operate as a memory cell at a first voltage level during a SRAM phase; and a controller controlling bit line signals on the plurality of bit lines and word line signals on the plurality of word lines, wherein the controller is configured to: during the RNG phase, precharge the plurality of bit lines to a second voltage level, and determine the initial logic states of the plurality of bit cells to generate at least one random number, wherein the second voltage level is lower than the first voltage level.