公开(公告)号：US12119052B2

公开(公告)日：2024-10-15

申请号：US18362736

申请日：2023-07-31

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Mahmut Sinangil ,  Yen-Huei Chen ,  Yen-Ting Lin ,  Hung-Jen Liao ,  Jonathan Tsung-Yung Chang

IPC: G11C11/419 ,  G11C11/418

CPC classification number: G11C11/419 ,  G11C11/418

Abstract: A twelve-transistor (12T) memory cell for a memory device that includes a transmission gate, a cross-coupled inverter circuit operably connected to the transmission gate, and a tri-state inverter operably connected to the cross-coupled inverter circuit. The cross-coupled inverter includes another tri-state inverter cross-coupled to an inverter circuit. Various operations for the 12T memory cell, as well as circuitry to perform the operations, are disclosed.

公开(公告)号：US12072750B2

公开(公告)日：2024-08-27

申请号：US18337449

申请日：2023-06-20

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chia-Chen Kuo ,  Yangsyu Lin ,  Yu-Hao Hsu ,  Cheng Hung Lee ,  Hung-Jen Liao

IPC: G06F1/32 ,  G06F1/3206 ,  G06F1/3234

CPC classification number: G06F1/3206 ,  G06F1/3275

Abstract: A circuit includes a power detector and a logic circuit. The power detector is configured to output a first power management signal according to a first power supply signal from a first power supply and a status signal. The circuit is configured to operate in different modes in response to the status signal. The logic circuit is configured to output a second power management signal, according to the first power management signal and the status signal.

公开(公告)号：US11910587B2

公开(公告)日：2024-02-20

申请号：US17410860

申请日：2021-08-24

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Hidehiro Fujiwara ,  Yi-Hsin Nien ,  Hung-Jen Liao

IPC: H10B10/00

CPC classification number: H10B10/18 ,  H10B10/12

Abstract: An apparatus includes memory cells. A first memory cell of the memory cells includes a first write port laid out in a first doping region and a first read port laid out in a second doping region. The first read port is separated from the first write port by a second write port of a second memory cell of the memory cells.

公开(公告)号：US11763882B2

公开(公告)日：2023-09-19

申请号：US17814700

申请日：2022-07-25

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Mahmut Sinangil ,  Yen-Huei Chen ,  Yen-Ting Lin ,  Hung-Jen Liao ,  Jonathan Tsung-Yung Chang

IPC: G11C11/419 ,  G11C11/418

CPC classification number: G11C11/419 ,  G11C11/418

Abstract: A twelve-transistor (12T) memory cell for a memory device that includes a transmission gate, a cross-coupled inverter circuit operably connected to the transmission gate, and a tri-state inverter operably connected to the cross-coupled inverter circuit. The cross-coupled inverter includes another tri-state inverter cross-coupled to an inverter circuit. Various operations for the 12T memory cell, as well as circuitry to perform the operations, are disclosed.

公开(公告)号：US11723195B2

公开(公告)日：2023-08-08

申请号：US17325708

申请日：2021-05-20

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Tsung-Hsien Huang ,  Hong-Chen Cheng ,  Hung-Jen Liao ,  Cheng Hung Lee

IPC: H01L27/112 ,  G11C7/18 ,  H10B20/00 ,  H01L23/522 ,  H01L21/768 ,  H01L23/528 ,  H01L27/06

CPC classification number: H10B20/50 ,  G11C7/18 ,  H01L21/76816 ,  H01L21/76877 ,  H01L23/5226 ,  H01L23/5283 ,  H01L27/0688 ,  H01L2924/0002 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method of making a semiconductor device includes forming a first memory device, connecting a first word line to the first memory device, forming at least a first via, forming a second memory device, connecting a second word line to the second memory device, connecting a bit line to the first memory device and connecting the bit line to the second memory device by the first via. The first and second memory devices are separated by an inter-layer dielectric, and the first via connects the first memory device and the second memory device.

公开(公告)号：US11715505B2

公开(公告)日：2023-08-01

申请号：US17816090

申请日：2022-07-29

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD. ,  TSMC CHINA COMPANY, LIMITED

Inventor： Yi-Tzu Chen ,  Ching-Wei Wu ,  Hau-Tai Shieh ,  Hung-Jen Liao ,  Fu-An Wu ,  He-Zhou Wan ,  XiuLi Yang

IPC: G11C7/22 ,  G11C7/10 ,  G11C7/12 ,  G11C7/14

CPC classification number: G11C7/222 ,  G11C7/106 ,  G11C7/1048 ,  G11C7/1087 ,  G11C7/12 ,  G11C7/14

Abstract: A memory circuit includes a NAND logic gate configured to receive a first bit line signal and a second bit line signal, and to generate a first signal. The memory circuit further includes a first N-type transistor coupled to the NAND logic gate, and configured to receive a first pre-charge signal. The memory circuit further includes a second N-type transistor coupled to the first N-type transistor and a reference voltage supply, and configured to receive a first clock signal. The memory circuit further includes a first latch coupled to the NAND logic gate, and configured to latch the first signal in response to at least the first clock signal or the first pre-charge signal.

公开(公告)号：US11562946B2

公开(公告)日：2023-01-24

申请号：US17209878

申请日：2021-03-23

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD. ,  TSMC NANJING COMPANY, LIMITED

Inventor： Hidehiro Fujiwara ,  Tze-Chiang Huang ,  Hong-Chen Cheng ,  Yen-Huei Chen ,  Hung-Jen Liao ,  Jonathan Tsung-Yung Chang ,  Yun-Han Lee ,  Lee-Chung Lu

IPC: G11C11/00 ,  H01L23/48 ,  G11C11/418 ,  H01L21/768 ,  H01L27/11

Abstract: A memory macro structure includes a first memory array, a second memory array, a cell activation circuit coupled to the first and second memory arrays and positioned between the first and second memory arrays, a control circuit coupled to the cell activation circuit and positioned adjacent to the cell activation circuit, and a through-silicon via (TSV) extending through one of the cell activation circuit or the control circuit.

公开(公告)号：US20220139450A1

公开(公告)日：2022-05-05

申请号：US17084635

申请日：2020-10-30

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Hidehiro Fujiwara ,  Hung-Jen Liao ,  Yen-Huei Chen

IPC: G11C11/419

Abstract: The disclosure introduces a write assist scheme that boost the word line of a selected memory cell by using a parasitic capacitor element coupled between the word line and a bit line of at least one unselected memory cell. The SRAM includes a word line, a first bit line, a second bit line, a first memory cell coupled to the first bit line and the word line, a second memory cell coupled to the second bit line and the word line, and a write assist circuit coupled to the second bit line. The write assist circuit is configured to clamp the second bit line to the word line during a write operation of the first memory cell.

公开(公告)号：US20220068355A1

公开(公告)日：2022-03-03

申请号：US17006882

申请日：2020-08-30

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Hua-Hsin Yu ,  Cheng-Hung Lee ,  Hung-Jen Liao ,  Hau-Tai Shieh

IPC: G11C11/4091 ,  G11C11/4074 ,  G11C11/4076 ,  G11C11/4099 ,  G11C7/10

Abstract: The disclosure is directed to a memory circuit, an electronic device, and a method of operating the memory circuit. According to an exemplary embodiment, the disclosure is directed to a memory circuit which includes not limited to a voltage equalizing circuit configured to equalize and pre-charge a first data line and a second data line to a reference voltage, a sense amplifier circuit configured to sense a binary data based on a relative voltage between the first data line and the second data line, a read-out latch circuit configured to receive the binary data which is to be transmitted to an external controller, and a write circuit configured to receive a first signal of the first data line and a second signal of the second data line so as to write the first signal to a first bit line and the second signal to a second bit line.

公开(公告)号：US20210263672A1

公开(公告)日：2021-08-26

申请号：US17130918

申请日：2020-12-22

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Jonathan Tsung-Yung Chang ,  Hidehiro Fujiwara ,  Hung-Jen Liao ,  Yen-Huei Chen ,  Yih Wang ,  Haruki Mori

IPC: G06F3/06 ,  G11C11/419

Abstract: A charge sharing scheme is used to mitigate the variations in cell currents in order to achieve higher accuracy for CIM computing. In some embodiments, a capacitor is associated with each SRAM cell, and the capacitors associated with all SRAM cells in a column are included in averaging the RBL current. In some embodiments, a memory unit associated to an RBL in a CIM device includes a storage element adapted to store a weight, a first switch device connected to the storage element and adapted to be controlled by an input signal and generate a product signal having a magnitude indicative of the product of the input signal and the stored weight. The memory unit further includes a capacitor adapted to receive the product signal and store an amount of charge corresponding to the magnitude of the product signal. The memory unit further include a second switch device adapted to transfer the charge on the capacitor to the RBL.