公开(公告)号：US12029023B2

公开(公告)日：2024-07-02

申请号：US18304301

申请日：2023-04-20

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Hidehiro Fujiwara ,  Chih-Yu Lin ,  Hsien-Yu Pan ,  Yasutoshi Okuno ,  Yen-Huei Chen ,  Hung-Jen Liao

IPC分类号： H10B10/00 ,  G06F30/392 ,  H01L23/522 ,  H01L23/528 ,  H01L27/02

CPC分类号： H10B10/12 ,  G06F30/392 ,  H01L23/5226 ,  H01L23/5286 ,  H01L27/0207

摘要： A method of forming a memory circuit includes generating a layout design of the memory circuit, and manufacturing the memory circuit based on the layout design. The generating of the layout design includes generating a first active region layout pattern corresponding to fabricating a first active region of a first pull down transistor, generating a second active region layout pattern corresponding to fabricating a second active region of a first pass gate transistor, and generating a first metal contact layout pattern corresponding to fabricating a first metal contact. The first metal contact layout pattern overlaps the cell boundary of the memory circuit and the first active region layout pattern. The first metal contact electrically coupled to a source of the first pull down transistor. The memory circuit being a four transistor (4T) memory cell including a first and second pass gate transistor, and a first and second pull down transistor.

公开(公告)号：US11929109B2

公开(公告)日：2024-03-12

申请号：US18306762

申请日：2023-04-25

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Yi-Tzu Chen ,  Ching-Wei Wu ,  Hau-Tai Shieh ,  Hung-Jen Liao

IPC分类号： G11C11/40 ,  G11C5/02 ,  G11C5/06 ,  G11C11/408 ,  G11C11/4093

CPC分类号： G11C11/4085 ,  G11C5/025 ,  G11C5/06 ,  G11C11/4093

摘要： Disclosed herein are related to a memory system including unit storage circuits. In one aspect, each of the unit storage circuits abuts an adjacent one of the unit storage circuits. In one aspect, each of the unit storage circuits includes a first group of memory cells, a second group of memory cells, a first sub-word line driver to apply a first control signal to the first group of memory cells through a first sub-word line extending along a direction, and a second sub-word line driver to apply a second control signal to the second group of memory cells through a second sub-word line extending along the direction. In one aspect, the memory system includes a common word line driver abutting one of the unit storage circuits and configured to apply a common control signal to the unit storage circuits through a word line extending along the direction.

公开(公告)号：US11798632B2

公开(公告)日：2023-10-24

申请号：US17313404

申请日：2021-05-06

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Manish Arora ,  Yen-Huei Chen ,  Hung-Jen Liao ,  Nikhil Puri ,  Yu-Hao Hsu

IPC分类号： G11C16/24 ,  G11C7/12 ,  G11C16/04 ,  G11C11/00 ,  H10B41/20 ,  H10B41/35

CPC分类号： G11C16/24 ,  G11C7/12 ,  G11C11/005 ,  G11C16/0483 ,  H10B41/20 ,  H10B41/35

摘要： A write line circuit includes a power supply node configured to carry a power supply voltage level, a reference node configured to carry a reference voltage level, an output node, first and second switching devices coupled in series between the output node and the power supply node, and a third switching device directly coupled to each of the output node and the reference node. The first switching device is configured to selectively couple the output node to the second switching device responsive to a first data signal, the second switching device is configured to selectively couple the first switching device to the power supply node responsive to a second data signal, and the third switching device is configured to selectively couple the output node to the reference node responsive to the first data signal.

公开(公告)号：US20220199145A1

公开(公告)日：2022-06-23

申请号：US17687272

申请日：2022-03-04

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Yi-Tzu Chen ,  Ching-Wei Wu ,  Hau-Tai Shieh ,  Hung-Jen Liao

IPC分类号： G11C11/408 ,  G11C5/02 ,  G11C11/4093 ,  G11C5/06

摘要： Disclosed herein are related to a memory system including unit storage circuits. In one aspect, each of the unit storage circuits abuts an adjacent one of the unit storage circuits. In one aspect, each of the unit storage circuits includes a first group of memory cells, a second group of memory cells, a first sub-word line driver to apply a first control signal to the first group of memory cells through a first sub-word line extending along a direction, and a second sub-word line driver to apply a second control signal to the second group of memory cells through a second sub-word line extending along the direction. In one aspect, the memory system includes a common word line driver abutting one of the unit storage circuits and configured to apply a common control signal to the unit storage circuits through a word line extending along the direction.

公开(公告)号：US20210287740A1

公开(公告)日：2021-09-16

申请号：US17334083

申请日：2021-05-28

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Wei-Cheng Wu ,  Hung-Jen Liao ,  Ping-Wei Wang ,  Wei Min Chan ,  Yen-Huei Chen

IPC分类号： G11C11/419 ,  G11C11/4063 ,  G11C11/409 ,  G11C11/41 ,  G11C11/412

摘要： A static random access memory (SRAM) includes a bit cell including a p-type pass gate, a bit information path connected to the bit cell by the p-type pass gate, and a read multiplexer connected to the bit information path. The read multiplexer includes an n-type transistor configured to selectively couple the bit information path to a sense amplifier.

公开(公告)号：US11043264B2

公开(公告)日：2021-06-22

申请号：US16884774

申请日：2020-05-27

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Wei-Cheng Wu ,  Wei Min Chan ,  Yen-Huei Chen ,  Hung-Jen Liao ,  Ping-Wei Wang

IPC分类号： G11C11/41 ,  G11C11/419 ,  G11C11/4063 ,  G11C11/409 ,  G11C11/412

摘要： A method of performing a write operation on a static random access memory (SRAM) bit cell includes activating the bit cell by supplying a signal to a p-type pass gate of the bit cell, the signal causing the p-type pass gate to be in a conductive state, using a p-type transistor of a write multiplexer to maintain a data line at a logically high voltage, and transferring bit information from the data line to the activated bit cell using the p-type pass gate.

公开(公告)号：US20210043252A1

公开(公告)日：2021-02-11

申请号：US17068150

申请日：2020-10-12

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Mahmut Sinangil ,  Yen-Huei Chen ,  Yen-Ting Lin ,  Hung-Jen Liao ,  Jonathan Tsung-Yung Chang

IPC分类号： G11C11/419 ,  G11C11/418

摘要： A twelve-transistor (12T) memory cell for a memory device that includes a transmission gate, a cross-coupled inverter circuit operably connected to the transmission gate, and a tri-state inverter operably connected to the cross-coupled inverter circuit. The cross-coupled inverter includes another tri-state inverter cross-coupled to an inverter circuit. Various operations for the 12T memory cell, as well as circuitry to perform the operations, are disclosed.

公开(公告)号：US10803928B2

公开(公告)日：2020-10-13

申请号：US16415554

申请日：2019-05-17

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Mahmut Sinangil ,  Yen-Huei Chen ,  Yen-Ting Lin ,  Hung-Jen Liao ,  Jonathan Tsung-Yung Chang

IPC分类号： G11C11/419 ,  G11C11/418

摘要： A twelve-transistor (12T) memory cell for a memory device that includes a transmission gate, a cross-coupled inverter circuit operably connected to the transmission gate, and a tri-state inverter operably connected to the cross-coupled inverter circuit. The cross-coupled inverter includes another tri-state inverter cross-coupled to an inverter circuit. Various operations for the 12T memory cell, as well as circuitry to perform the operations, are disclosed.

公开(公告)号：US20190326302A1

公开(公告)日：2019-10-24

申请号：US16458970

申请日：2019-07-01

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Yen-Huei Chen ,  Hung-Jen Liao ,  Chih-Yu Lin ,  Jonathan Tsung-Yung Chang ,  Wei-Cheng Wu

IPC分类号： H01L27/11 ,  H01L49/02 ,  H01L23/522 ,  H01L23/532 ,  G11C11/419 ,  G11C11/412 ,  H01L23/528

摘要： A memory circuit including: a first column of memory cells, each memory cell of the first column including a first supply segment; a first supply voltage line in a first conductive layer, the first supply voltage line being made of at least the first supply segments of the first column; a second supply voltage line; a first resistive device electrically connecting the first and second supply voltage lines, and being located in a via layer; a first material, from which the first resistive device is formed, being different than a second material from which a first type of via plug in the via layer is formed; and a supply voltage source electrically coupled with first supply voltage line through one or more conductive paths, and the second supply voltage line and the first resistive device being in a lowest resistance path of the one or more conductive paths.

公开(公告)号：US10163491B2

公开(公告)日：2018-12-25

申请号：US15251260

申请日：2016-08-30

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Hidehiro Fujiwara ,  Li-Wen Wang ,  Yen-Huei Chen ,  Hung-Jen Liao

IPC分类号： G11C8/14 ,  G11C11/419 ,  G11C11/418 ,  H01L27/02 ,  H01L27/11

摘要： A memory circuit includes first and second memory cells. The first memory cell has an access port having a pass gate. The second memory cell also has an access port having a pass gate. The first and second memory cells abut one another along a column direction. The circuit includes at least one conductive structure over the first and second memory cells. The conductive structure may be two interconnected conductive lines. The conductive structure extends along a row direction in a conductive layer and is electrically coupled to the gate terminals of the pass gates.