A circuit for a divider or counter may include a frequency divider having multiple rings for dividing an input frequency to obtain an output frequency. The first and second rings may include an odd-numbered plurality of elements, such as inverters, wherein each inverter of a ring is coupled to another inverter of the ring in a circular chain. An input frequency may be input to a power supply input of inverters of the first ring. The second ring inverters may be coupled at a power supply input to output nodes of the first ring inverters, which results in the second ring operating at a divisional rate of the first frequency given by (N−1), where N is the number of inverters in the ring. The circuits may be used in frequency dividers and counters, such as in phase-locked loops (PLLs) and analog-to-digital converters (ADCs).