Invention Grant
- Patent Title: Uncertainty aware interconnect design to improve circuit performance and/or yield
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Application No.: US14707859Application Date: 2015-05-08
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Publication No.: US09608602B2Publication Date: 2017-03-28
- Inventor: Chunchen Liu , Oscar Ming Kin Law , Ju-Yi Lu , Po-Hung Chen , Zhengyu Duan
- Applicant: QUALCOMM Incorporated
- Applicant Address: US CA San Diego
- Assignee: QUALCOMM Incorporated
- Current Assignee: QUALCOMM Incorporated
- Current Assignee Address: US CA San Diego
- Agency: Loza & Loza, LLP
- Main IPC: H03L7/00
- IPC: H03L7/00 ; H03K3/03 ; H03K3/012 ; H01L27/118 ; G06F17/50 ; H01L27/02 ; G01R31/3193 ; H03K19/003

Abstract:
Methods and an apparatus related to generating parameters and guidelines used in the manufacture of semiconductor IC devices are described. A method includes measuring a first oscillating signal produced by a first ring oscillator that includes a first interconnect provided in a first interconnect layer of an IC, selecting a first mode of operation for a second ring oscillator circuit that includes a second interconnect disposed in alignment with the first interconnect, selecting a second mode of operation for the second ring oscillator circuit, and determining one or more characteristics of the first interconnect based on a difference in frequency of the first oscillating signal produced when the second ring oscillator circuit is operated in the first mode and frequency of the first oscillating signal when the second ring oscillator circuit is operated in the second mode.
Public/Granted literature
- US20160329882A1 UNCERTAINTY AWARE INTERCONNECT DESIGN TO IMPROVE CIRCUIT PERFORMANCE AND/OR YIELD Public/Granted day:2016-11-10
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