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    Hybrid three-dimensional integrated circuit reconfigurable thermal aware and dynamic power gating interconnect architecture
    1.
    发明授权
    Hybrid three-dimensional integrated circuit reconfigurable thermal aware and dynamic power gating interconnect architecture 有权

    公开(公告)号：US10224310B2

    公开(公告)日：2019-03-05

    申请号：US15336576

    申请日：2016-10-27

    Applicant: QUALCOMM Incorporated

    Inventor： Chunchen Liu

    IPC: H03K17/14 ,  H01L25/065 ,  B23K11/24 ,  H02B1/24 ,  G11C8/12

    Abstract: Systems, methods, and apparatus for operating an integrated circuit (IC) are provided. An apparatus may be configured to receive at one or more switches a signal from at least one circuit positioned on a first die lying within a first geometric plane, detect a signaling path between the at least one circuit positioned on the first die and at least one circuit positioned on a second die lying within a second geometric plane that is different from the first geometric plane, and control the one or more switches to route the signal along the signaling path. Circuits having a similar power characteristic are positioned adjacent to each other on the first die or the second die and circuits having a high temperature characteristic are positioned separate from each other on the first die or the second die.

    TEMPERATURE-BASED WIRE ROUTING
    6.
    发明申请
    TEMPERATURE-BASED WIRE ROUTING 审中-公开
    基于温度的线路

    公开(公告)号：US20150227667A1

    公开(公告)日：2015-08-13

    申请号：US14175429

    申请日：2014-02-07

    Applicant: QUALCOMM Incorporated

    Inventor： Chunchen Liu

    IPC: G06F17/50 ,  H05K3/00 ,  H05K1/02

    CPC classification number: G06F17/5077 ,  G06F2217/80 ,  G06F2217/84 ,  H05K1/0201 ,  H05K1/0296 ,  H05K3/0005 ,  Y10T29/49162

    Abstract: A circuit design scheme routes wires based on temperature. In particular, temperature conditions along a prospective route are taken into account when determining whether to use that route for a wire. For example, a route can be selected from among a set of prospective routes based on which route is associated with the “smoothest” temperature gradient. Here, preference may be given to the route or routes having the smallest amount of temperature variation along the route.

    Abstract translation: 电路设计方案基于温度来布线。 特别地，当确定是否将该路线用于电线时，将考虑沿着预期路线的温度条件。 例如，可以基于哪个路线与“最平滑的”温度梯度相关联的一组预期路线中的路线选择。 这里，可以优选沿着路线具有最小温度变化量的路线或路线。

    UNCERTAINTY AWARE INTERCONNECT DESIGN TO IMPROVE CIRCUIT PERFORMANCE AND/OR YIELD
    8.
    发明申请
    UNCERTAINTY AWARE INTERCONNECT DESIGN TO IMPROVE CIRCUIT PERFORMANCE AND/OR YIELD 有权
    不确定性互连设计，以提高电路性能和/或电流

    公开(公告)号：US20160329882A1

    公开(公告)日：2016-11-10

    申请号：US14707859

    申请日：2015-05-08

    Applicant: QUALCOMM Incorporated

    Inventor： Chunchen Liu ,  Oscar Ming Kin Law ,  Ju-Yi Lu ,  Po-Hung Chen ,  Zhengyu Duan

    IPC: H03K3/03 ,  H03K3/012

    CPC classification number: H03K3/0315 ,  G01R31/31937 ,  G06F17/5045 ,  G06F17/5068 ,  G06F17/5081 ,  H01L27/0207 ,  H01L27/11807 ,  H03K3/012 ,  H03K19/00346

    Abstract: Methods and an apparatus related to generating parameters and guidelines used in the manufacture of semiconductor IC devices are described. A method includes measuring a first oscillating signal produced by a first ring oscillator that includes a first interconnect provided in a first interconnect layer of an IC, selecting a first mode of operation for a second ring oscillator circuit that includes a second interconnect disposed in alignment with the first interconnect, selecting a second mode of operation for the second ring oscillator circuit, and determining one or more characteristics of the first interconnect based on a difference in frequency of the first oscillating signal produced when the second ring oscillator circuit is operated in the first mode and frequency of the first oscillating signal when the second ring oscillator circuit is operated in the second mode.

    Abstract translation: 描述了与用于制造半导体IC器件的参数和指导相关的方法和装置。 一种方法包括测量由第一环形振荡器产生的第一振荡信号，所述第一振荡信号包括设置在IC的第一互连层中的第一互连，为第二环形振荡器电路选择第一工作模式，所述第二环路振荡器电路包括与第 所述第一互连，为所述第二环形振荡器电路选择第二操作模式，以及基于当所述第二环形振荡器电路在所述第一环形振荡器中运行时产生的所述第一振荡信号的频率差，确定所述第一互连的一个或多个特性 当第二环形振荡器电路在第二模式下操作时，第一振荡信号的模式和频率。

    OPTIMIZING INTERCONNECT DESIGNS IN LOW-POWER INTEGRATED CIRCUITS (ICs)
    9.
    发明申请
    OPTIMIZING INTERCONNECT DESIGNS IN LOW-POWER INTEGRATED CIRCUITS (ICs) 审中-公开
    低功耗集成电路（IC）优化互连设计

    公开(公告)号：US20160275227A1

    公开(公告)日：2016-09-22

    申请号：US14658504

    申请日：2015-03-16

    Applicant: QUALCOMM Incorporated

    Inventor： Chunchen Liu ,  Ju-Yi Lu ,  Shengqiong Xie

    IPC: G06F17/50

    CPC classification number: G06F17/5072 ,  G06F1/3287 ,  G06F17/5077 ,  G06F2217/78

    Abstract: Aspects disclosed in the detailed description include optimizing interconnect designs in low-power integrated circuits (ICs). In this regard, in one aspect, functional blocks having substantially correlated power utilization patterns are grouped into a power-related cluster to share a sleeping cell, thus leading to a reduced number of sleep transistors and a simplified interconnect design in a low-power IC. In another aspect, functional blocks having higher block temperatures are separated into more than one power-related cluster, improving heat dissipation in the low-power IC. A simulated annealing (SA) process is employed to determine an optimized placement for the low-power IC based on a power-related cost function that includes a power-related parameter and a heat-related parameter. By running the SA process based on the power-related cost function, it is possible to determine the optimized placement that leads to the reduced number of sleep transistors and improved heat dissipation in the low-power IC.

    Abstract translation: 在详细描述中公开的方面包括优化低功率集成电路（IC）中的互连设计。 在这方面，在一个方面，具有基本上相关的功率利用模式的功能块被分组成功率相关的簇以共享睡眠小区，从而导致在低功率IC中减少数量的睡眠晶体管和简化的互连设计 。 在另一方面，具有较高块温度的功能块被分离成多于一个功率相关的簇，从而改善了低功率IC中的散热。 采用模拟退火（SA）工艺来确定基于功率相关成本函数的低功率IC的优化布局，该功能包括功率相关参数和热相关参数。 通过运行基于功率相关成本函数的SA过程，可以确定导致低功率IC中减少睡眠晶体管数量和改善散热的优化布局。

    3D INTEGRATED CIRCUIT
    10.
    发明申请
    3D INTEGRATED CIRCUIT 有权
    3D集成电路

    公开(公告)号：US20160211241A1

    公开(公告)日：2016-07-21

    申请号：US14598052

    申请日：2015-01-15

    Applicant: QUALCOMM Incorporated

    Inventor： Oscar Law ,  Chunchen Liu ,  Ju-Yi Lu

    IPC: H01L25/065 ,  H03K17/56 ,  H03K17/00

    CPC classification number: H01L25/0657 ,  G01R31/318513 ,  G11C29/1201 ,  G11C29/48 ,  H01L22/32 ,  H01L23/5384 ,  H01L23/5385 ,  H01L2224/13025 ,  H01L2224/16146 ,  H01L2224/16227 ,  H01L2224/17181 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06572 ,  H01L2225/06596 ,  H01L2924/0002 ,  H03K17/002 ,  H03K17/56 ,  H01L2924/00

    Abstract: A three-dimensional integrated circuit (3D-IC) architecture incorporates multiple layers, each layer including at least one die and at least one switch to connect the dies on the different layers. In some aspects, a power distribution network (PDN) is routed from a first layer through the switches to supply power to at least one other layer, thereby reducing routing congestion on the layers. The switches can be placed around the periphery of an IC package to improve heat dissipation (e.g., by improving heat transfer from the center to the edge of the IC package). The switches can be used for routing test signals and/or other signals between layers, thereby improving test functionality and/or fault recovery.

    Abstract translation: 三维集成电路（3D-IC）架构结合了多个层，每个层包括至少一个管芯和至少一个开关以连接不同层上的管芯。 在一些方面，配电网络（PDN）从第一层通过交换机路由到至少一个其他层供电，从而减少层上的路由拥塞。 开关可以放置在IC封装的周围，以改善散热（例如，通过改善从IC封装的中心到边缘的热传递）。 交换机可以用于在层之间路由测试信号和/或其他信号，从而提高测试功能和/或故障恢复。

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