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    UNCERTAINTY AWARE INTERCONNECT DESIGN TO IMPROVE CIRCUIT PERFORMANCE AND/OR YIELD
    2.
    发明申请
    UNCERTAINTY AWARE INTERCONNECT DESIGN TO IMPROVE CIRCUIT PERFORMANCE AND/OR YIELD 有权
    不确定性互连设计，以提高电路性能和/或电流

    公开(公告)号：US20160329882A1

    公开(公告)日：2016-11-10

    申请号：US14707859

    申请日：2015-05-08

    Applicant: QUALCOMM Incorporated

    Inventor： Chunchen Liu ,  Oscar Ming Kin Law ,  Ju-Yi Lu ,  Po-Hung Chen ,  Zhengyu Duan

    IPC: H03K3/03 ,  H03K3/012

    CPC classification number: H03K3/0315 ,  G01R31/31937 ,  G06F17/5045 ,  G06F17/5068 ,  G06F17/5081 ,  H01L27/0207 ,  H01L27/11807 ,  H03K3/012 ,  H03K19/00346

    Abstract: Methods and an apparatus related to generating parameters and guidelines used in the manufacture of semiconductor IC devices are described. A method includes measuring a first oscillating signal produced by a first ring oscillator that includes a first interconnect provided in a first interconnect layer of an IC, selecting a first mode of operation for a second ring oscillator circuit that includes a second interconnect disposed in alignment with the first interconnect, selecting a second mode of operation for the second ring oscillator circuit, and determining one or more characteristics of the first interconnect based on a difference in frequency of the first oscillating signal produced when the second ring oscillator circuit is operated in the first mode and frequency of the first oscillating signal when the second ring oscillator circuit is operated in the second mode.

    Abstract translation: 描述了与用于制造半导体IC器件的参数和指导相关的方法和装置。 一种方法包括测量由第一环形振荡器产生的第一振荡信号，所述第一振荡信号包括设置在IC的第一互连层中的第一互连，为第二环形振荡器电路选择第一工作模式，所述第二环路振荡器电路包括与第 所述第一互连，为所述第二环形振荡器电路选择第二操作模式，以及基于当所述第二环形振荡器电路在所述第一环形振荡器中运行时产生的所述第一振荡信号的频率差，确定所述第一互连的一个或多个特性 当第二环形振荡器电路在第二模式下操作时，第一振荡信号的模式和频率。

    High-speed word line decoder and level-shifter
    4.
    发明授权
    High-speed word line decoder and level-shifter 有权

    公开(公告)号：US09940987B2

    公开(公告)日：2018-04-10

    申请号：US15070963

    申请日：2016-03-15

    Applicant: QUALCOMM Incorporated

    Inventor： Chulmin Jung ,  Po-Hung Chen ,  David Li ,  Sei Seung Yoon

    IPC: G11C7/00 ,  G11C8/08 ,  G11C8/10 ,  G11C8/06 ,  G11C5/14

    CPC classification number: G11C8/08 ,  G11C5/14 ,  G11C8/06 ,  G11C8/10

    Abstract: A memory is provided that includes a row decoder that decodes an address into a plurality of decoded signals for selecting a word line to be asserted from a plurality of word lines. Each word line is driven through a decoder level-shifter that processes the decoded signals. Each decoder level-shifter corresponds to a unique combination of the decoded signals. The row decoder is in a logic power domain such that the decoded signals are asserted to a logic power supply voltage. When a decoder level-shifter's unique combination of decoded signals are asserted by the row decoder, the decoder level-shifter drives the corresponding word line with a memory power supply voltage for a memory power domain.

    Memory circuit architecture
    8.
    发明授权
    Memory circuit architecture 有权

    公开(公告)号：US11600307B2

    公开(公告)日：2023-03-07

    申请号：US17136616

    申请日：2020-12-29

    Applicant: QUALCOMM Incorporated

    Inventor： David Li ,  Rahul Biradar ,  Biju Manakkam Veetil ,  Po-Hung Chen ,  Ayan Paul ,  Sung Son ,  Shivendra Kushwaha ,  Ravindra Reddy Chekkera ,  Derek Yang

    IPC: G11C5/02 ,  G11C7/06 ,  G11C7/10 ,  G11C8/08 ,  G11C8/10

    Abstract: A semiconductor device includes: a memory circuit having a plurality of quadrants arranged at corners of the memory circuit and surrounding a bank control component; wherein a first quadrant of the plurality of quadrants includes a first bit cell core and a first set of input output circuits configured to access the first bit cell core, the first quadrant defined by a rectangular boundary that encloses portions of two perpendicular edges of the memory circuit; wherein a second quadrant of the plurality of quadrants includes a second bit cell core and a second set of input output circuits configured to access the second bit cell core, the second quadrant being adjacent the first quadrant, wherein a border between the first quadrant and the second quadrant defines a first axis about which the first quadrant and the second quadrant are symmetrical.

    High-speed level shifter
    9.
    发明授权
    High-speed level shifter 有权

    公开(公告)号：US09997208B1

    公开(公告)日：2018-06-12

    申请号：US15473124

    申请日：2017-03-29

    Applicant: QUALCOMM Incorporated

    Inventor： Chulmin Jung ,  Po-Hung Chen ,  Fahad Ahmed ,  Changho Jung ,  Sei Seung Yoon ,  David Li

    IPC: G11C8/08 ,  G11C5/14 ,  H03K19/0185 ,  G11C8/10 ,  G11C7/12

    CPC classification number: G11C5/147 ,  G11C7/12 ,  G11C8/10 ,  H03K3/356069 ,  H03K19/018528

    Abstract: A circuit including an output node and a cross-coupled pair of semiconductor devices configured to provide, at the output node, an output signal in a second voltage domain based on an input signal in a first voltage domain is described herein. The circuit further includes a pull-up assist circuit coupled to the output node; and a look-ahead circuit coupled to the pull-up assist circuit, wherein the look-ahead circuit is configured to cause the pull-up assist circuit to assist in increasing a voltage level at the output node when there is a decrease in a voltage level of an inverted output signal in the second voltage domain from a high voltage level of the second voltage domain to a low voltage level of the second voltage domain.

    HIGH-SPEED WORD LINE DECODER AND LEVEL-SHIFTER
    10.
    发明申请
    HIGH-SPEED WORD LINE DECODER AND LEVEL-SHIFTER 有权
    高速字线解码器和电平变换器

    公开(公告)号：US20160276005A1

    公开(公告)日：2016-09-22

    申请号：US15070963

    申请日：2016-03-15

    Applicant: QUALCOMM Incorporated

    Inventor： Chulmin Jung ,  Po-Hung Chen ,  David Li ,  Sei Seung Yoon

    IPC: G11C8/08 ,  G11C8/10 ,  G11C5/14

    CPC classification number: G11C8/08 ,  G11C5/14 ,  G11C8/06 ,  G11C8/10

    Abstract: A memory is provided that includes a row decoder that decodes an address into a plurality of decoded signals for selecting a word line to be asserted from a plurality of word lines. Each word line is driven through a decoder level-shifter that processes the decoded signals. Each decoder level-shifter corresponds to a unique combination of the decoded signals. The row decoder is in a logic power domain such that the decoded signals are asserted to a logic power supply voltage. When a decoder level-shifter's unique combination of decoded signals are asserted by the row decoder, the decoder level-shifter drives the corresponding word line with a memory power supply voltage for a memory power domain.

    Abstract translation: 提供了一种存储器，其包括行解码器，其将地址解码为用于从多个字线选择要断言的字线的多个解码信号。 每个字线通过处理解码信号的解码器电平转换器驱动。 每个解码器电平转换器对应于解码信号的唯一组合。 行解码器处于逻辑功率域，使得解码信号被断言为逻辑电源电压。 当解码器电平移位器的解码信号的唯一组合由行解码器确定时，解码器电平转换器用存储器电源域的存储器电源电压驱动相应的字线。

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