Invention Grant
- Patent Title: Techniques and configurations associated with a package load assembly
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Application No.: US14484896Application Date: 2014-09-12
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Publication No.: US09615483B2Publication Date: 2017-04-04
- Inventor: Gaurav Chawla , Joshua D. Heppner , Vijaykumar Krithivasan , Michael Garcia , Kuang C. Liu , Rajasekaran Swaminathan
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Schwabe, Williamson & Wyatt. P.C.
- Main IPC: H05K7/20
- IPC: H05K7/20 ; H01L23/367 ; H01L23/40 ; H01L23/433

Abstract:
Embodiments of the present disclosure are directed toward techniques and configurations associated with a package load assembly. In one embodiment, a package load assembly may include a frame configured to form a perimeter around a die area of a package substrate having a first surface configured to be coupled with a surface of the package substrate and a second surface disposed opposite to the first surface. The frame may include deformable members disposed on the second surface, which may be configured to be coupled with a base of a heat sink to distribute force applied between the heat sink and the package substrate, via the frame, and may deform under application of the force, which may allow the base of the heat sink to contact a surface of an integrated heat spreader within the die area of the package substrate.
Public/Granted literature
- US20160079150A1 TECHNIQUES AND CONFIGURATIONS ASSOCIATED WITH A PACKAGE LOAD ASSEMBLY Public/Granted day:2016-03-17
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