Invention Grant
- Patent Title: Hardware and runtime coordinated load balancing for parallel applications
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Application No.: US14641220Application Date: 2015-03-06
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Publication No.: US09619290B2Publication Date: 2017-04-11
- Inventor: Peter Bailey , Indrani Paul , Manish Arora
- Applicant: Advanced Micro Devices, Inc.
- Applicant Address: US CA Sunnyvale
- Assignee: Advanced Micro Devices, Inc.
- Current Assignee: Advanced Micro Devices, Inc.
- Current Assignee Address: US CA Sunnyvale
- Agency: Liang & Cheng, PC
- Main IPC: G06F9/46
- IPC: G06F9/46 ; G06F9/50 ; G06F9/45

Abstract:
A method of balancing execution rates for a plurality of parallel program loops being executed concurrently by a processor may include estimating a completion time for each program loop of the plurality of program loops, determining a difference between the estimated completion time of a first program loop of the plurality of program loops and the estimated completion time of a second program loop of the plurality of program loops, and decreasing the difference by adjusting an execution rate of the first program loop.
Public/Granted literature
- US20160259667A1 HARDWARE AND RUNTIME COORDINATED LOAD BALANCING FOR PARALLEL APPLICATIONS Public/Granted day:2016-09-08
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