公开(公告)号：US12111716B2

公开(公告)日：2024-10-08

申请号：US18304849

申请日：2023-04-21

Applicant: Advanced Micro Devices, Inc.

Inventor： Mihir Shaileshbhai Doctor ,  Alexander J. Branover ,  Benjamin Tsien ,  Indrani Paul ,  Christopher T. Weaver ,  Thomas J. Gibney ,  Stephen V. Kosonocky ,  John P. Petry

IPC: G06F1/32 ,  G06F1/3234 ,  G06F1/3287 ,  G06F1/3296

CPC classification number: G06F1/3287 ,  G06F1/3265 ,  G06F1/3278 ,  G06F1/3296

Abstract: A processing device and method for efficient transitioning to and from a reduced power state is provided. The processing device comprises a plurality of components having assigned registers used to store data to execute a program and a power management controller, in communication with the plurality of components. The power management controller receives an indication that the plurality of components are idle, executes a process to enter a component into a reduced power state in response to receiving an acknowledgement from the component of a request from the power management controller to remove power to the component, and executes a process to exit the component from the reduced power state in response to the component being active.

公开(公告)号：US12086009B2

公开(公告)日：2024-09-10

申请号：US17710521

申请日：2022-03-31

Applicant: Advanced Micro Devices, Inc.

Inventor： Alexander J. Branover ,  Thomas J. Gibney ,  Mihir Shaileshbhai Doctor ,  Indrani Paul ,  Benjamin Tsien ,  Stephen V. Kosonocky ,  John P. Petry ,  Christopher T. Weaver

IPC: G06F1/32 ,  G06F1/3234

CPC classification number: G06F1/3234

Abstract: Methods and systems are disclosed for transitioning, by a hardware-based controller, a system on a chip (SoC) into different power states. Techniques disclosed include tracking, by the controller, metrics associated with the SoC and transitioning, by the controller, the SoC from a first power state to a second power state based on the tracked metrics. Were the total amount of power that is used by at least a portion of the transition between the first power state to the second power state and a time spent in the second power state is less than the total amount of power that would have been used by remaining in the first power state.

公开(公告)号：US20240235376A1

公开(公告)日：2024-07-11

申请号：US18478485

申请日：2023-09-29

Applicant: Advanced Micro Devices, Inc. ,  ATI Technologies ULC

Inventor： David King Wai Li ,  Amanullah Samit ,  Indrani Paul ,  Meeta Surendramohan Srivastav ,  Sriram Sambamurthy

IPC: H02M1/32 ,  H02M3/02

CPC classification number: H02M1/32 ,  H02M3/02

Abstract: The disclosed voltage regulator circuit includes a capacitor bank configured for a first voltage step corresponding to a voltage undershoot, and a shunt circuit configured for a second voltage step exceeding the first voltage step. Various other methods, systems, and computer-readable media are also disclosed.

公开(公告)号：US11714442B2

公开(公告)日：2023-08-01

申请号：US17560823

申请日：2021-12-23

Applicant: Advanced Micro Devices, Inc. ,  ATI Technologies ULC

Inventor： Meeta Surendramohan Srivastav ,  Ashwini Chandrashekhara Holla ,  Alex Sabino Duenas ,  Xinzhe Li ,  Michael John Austin ,  Indrani Paul ,  Sriram Sambamurthy

IPC: G06F1/28 ,  G05F1/66

CPC classification number: G05F1/66 ,  G06F1/28

Abstract: An electronic device includes an accelerated processing unit (APU) and multiple elements. The APU performs operations for a platform boost and throttle (PBT) controller. For the operations, the APU receives a platform electrical power limit, the platform electrical power limit being a limit on a total electrical power allowed to be consumed by a group of the elements at a given time. The APU then determines a present platform electrical power consumption. The APU next adjusts one or more operating parameters for specified elements from among the group of elements to control electrical power consumption by the specified elements based on a relationship between the present platform electrical power consumption and the platform electrical power limit.

公开(公告)号：US11703930B2

公开(公告)日：2023-07-18

申请号：US17381664

申请日：2021-07-21

Applicant: Advanced Micro Devices, Inc. ,  ATI Technologies ULC

Inventor： Indrani Paul ,  Sriram Sambamurthy ,  Larry David Hewitt ,  Kevin M. Lepak ,  Samuel D. Naffziger ,  Adam Neil Calder Clark ,  Aaron Joseph Grenat ,  Steven Frederick Liepe ,  Sandhya Shyamasundar ,  Wonje Choi ,  Dana Glenn Lewis ,  Leonardo de Paula Rosa Piga

IPC: G06F1/00 ,  G06F1/3225 ,  G06F1/3234 ,  G06F1/3203 ,  G06F1/26

CPC classification number: G06F1/3225 ,  G06F1/3275 ,  G06F1/26 ,  G06F1/3203

Abstract: Platform power management includes boosting performance in a platform power boost mode or restricting performance to keep a power or temperature under a desired threshold in a platform power cap mode. Platform power management exploits the mutually exclusive nature of activities and the associated headroom created in a temperature and/or power budget of a server platform to boost performance of a particular component while also keeping temperature and/or power below a threshold or budget.

公开(公告)号：US20230099399A1

公开(公告)日：2023-03-30

申请号：US17485199

申请日：2021-09-24

Applicant: Advanced Micro Devices, Inc.

Inventor： Alexander J. Branover ,  Christopher T. Weaver ,  Indrani Paul ,  Benjamin Tsien ,  Mihir Shaileshbhai Doctor ,  Stephen V. Kosonocky ,  John P. Petry ,  Thomas J. Gibney

IPC: G06F1/3296

Abstract: A method and apparatus for managing a controller includes indicating, by a processor of a first device, to the controller of a second device to enter a second power state from a first power state. The controller of the second device responds to the processor of the first device with a confirmation. The processor of the first device transmits a signal to the controller of the second device to enter the second power state. Upon receiving a wake event, the controller of the second device exits the second device from the second power state to the first power state.

公开(公告)号：US20230090567A1

公开(公告)日：2023-03-23

申请号：US17483702

申请日：2021-09-23

Applicant: Advanced Micro Devices, Inc.

Inventor： Benjamin Tsien ,  Alexander J. Branover ,  Indrani Paul ,  Christopher T. Weaver ,  Thomas J. Gibney ,  Stephen V. Kosonocky ,  John P. Petry ,  Mihir Shaileshbhai Doctor

IPC: G06F1/3234

Abstract: Devices and methods for cache prefetching are provided. A device is provided which comprises a quality of service (QOS) component having first assigned registers used to store data to execute a program, a plurality of non-QOS components having second assigned registers used to store data to execute the program and a power management controller, in communication with the QOS component and the non-QOS components. The power management controller is configured to issue fences for the non-QOS components when it is determined that one or more of the non-QOS components are idle, issue a fence for the QOS component when the fences for the non-QOS components are completed and enter a reduced power state when the fences for the non-QOS components and the fence for the QOS component are completed.

公开(公告)号：US20230088994A1

公开(公告)日：2023-03-23

申请号：US17993562

申请日：2022-11-23

Applicant: ADVANCED MICRO DEVICES, INC. ,  ATI TECHNOLOGIES ULC

Inventor： Karthik RAO ,  Indrani Paul ,  Donny YI ,  Oleksandr KHODORKOVSKY ,  Leonardo DE PAULA ROSA PIGA ,  Wonje CHOI ,  Dana G. LEWIS ,  Sriram SAMBAMURTHY

IPC: G06F1/3287

Abstract: An apparatus includes a processor, a sleep state duration prediction module, and a system management unit. The sleep state duration prediction module is configured to predict a sleep state duration for component of the processing device. The system management unit is to transition the component into a sleep state selected from a plurality of sleep states based on a comparison of the predicted sleep state duration to at least one duration threshold. Each sleep state of the plurality of sleep states is a lower power state than a previous sleep state of the plurality of sleep states.

公开(公告)号：US20230030985A1

公开(公告)日：2023-02-02

申请号：US17390486

申请日：2021-07-30

Applicant: Advanced Micro Devices, Inc.

Inventor： John P. Petry ,  Alexander J. Branover ,  Benjamin Tsien ,  Christopher T. Weaver ,  Stephen V. Kosonocky ,  Indrani Paul ,  Thomas J. Gibney ,  Mihir Shaileshbhai Doctor

IPC: G06F1/3287

Abstract: A disclosed technique includes triggering a change for a first set of one or more functional elements and for a second set of one or more functional elements from a high-power state to a low-power state; saving first state of the first set of one or more functional elements via a first set of one or more save-state elements; saving second state of the second set of one or more functional elements via a second set of one or more save-state elements; powering down the first set of one or more functional elements and the second set of one or more functional elements; and transmitting the first state and the second state to a memory.

公开(公告)号：US10025361B2

公开(公告)日：2018-07-17

申请号：US14297208

申请日：2014-06-05

Applicant: Advanced Micro Devices, Inc.

Inventor： Indrani Paul ,  Vignesh Trichy Ravi ,  Manish Arora ,  Srilatha Manne

IPC: G06F1/00 ,  G06F1/20 ,  G06F1/32 ,  G06F11/30 ,  G06F9/50 ,  G06F11/34

Abstract: A method includes controlling active frequency states of a plurality of heterogeneous processing units based on frequency sensitivity metrics indicating performance coupling between different types of processing units in the plurality of heterogeneous processing units. A processor includes a plurality of heterogeneous processing units and a performance controller to control active frequency states of the plurality of heterogeneous processing units based on frequency sensitivity metrics indicating performance coupling between different types of processing units in the plurality of heterogeneous processing units. The active frequency state of a first type of processing unit in the plurality of heterogeneous processing units is controlled based on a first activity metric associated with a first type of processing unit and a second activity metric associated with a second type of processing unit.