公开(公告)号：US10025361B2

公开(公告)日：2018-07-17

申请号：US14297208

申请日：2014-06-05

Applicant: Advanced Micro Devices, Inc.

Inventor： Indrani Paul ,  Vignesh Trichy Ravi ,  Manish Arora ,  Srilatha Manne

IPC: G06F1/00 ,  G06F1/20 ,  G06F1/32 ,  G06F11/30 ,  G06F9/50 ,  G06F11/34

Abstract: A method includes controlling active frequency states of a plurality of heterogeneous processing units based on frequency sensitivity metrics indicating performance coupling between different types of processing units in the plurality of heterogeneous processing units. A processor includes a plurality of heterogeneous processing units and a performance controller to control active frequency states of the plurality of heterogeneous processing units based on frequency sensitivity metrics indicating performance coupling between different types of processing units in the plurality of heterogeneous processing units. The active frequency state of a first type of processing unit in the plurality of heterogeneous processing units is controlled based on a first activity metric associated with a first type of processing unit and a second activity metric associated with a second type of processing unit.

公开(公告)号：US09946319B2

公开(公告)日：2018-04-17

申请号：US14059384

申请日：2013-10-21

Applicant: Advanced Micro Devices, Inc.

Inventor： Indrani Paul ,  Manish Arora ,  Srilatha Manne ,  William L. Bircher

IPC: G06F1/32 ,  G06F1/20

CPC classification number: G06F1/3206 ,  G06F1/206

Abstract: The described embodiments include a computing device with a first entity and a second entity. In the computing device, a management controller dynamically sets a power-state limit for the first entity based on a performance coupling and a thermal coupling between the first entity and the second entity.

公开(公告)号：US09720487B2

公开(公告)日：2017-08-01

申请号：US14152826

申请日：2014-01-10

Applicant: Advanced Micro Devices, Inc.

Inventor： William L. Bircher ,  Madhu Saravana Sibi Govindan ,  Manish Arora ,  Michael J. Schulte ,  Nuwan S. Jayasena

IPC: G06F1/32

CPC classification number: G06F1/3243 ,  G06F1/3287 ,  G06F1/329 ,  Y02D10/152 ,  Y02D10/171 ,  Y02D10/24 ,  Y02D50/20

Abstract: Durations of power management states are predicted on a per-process basis. Some embodiments include storing, in one or more data structures associated with one or more processes, information indicating previous durations of a power management state associated with the process(es). Some embodiments also include predicting a subsequent duration of the power management state for the process(es) using information stored in the data structure(s).

公开(公告)号：US20170083065A1

公开(公告)日：2017-03-23

申请号：US14862044

申请日：2015-09-22

Applicant: Advanced Micro Devices, Inc.

Inventor： Wei Huang ,  Manish Arora ,  Yasuko Eckert ,  Indrani Paul

IPC: G06F1/20 ,  G06F1/32 ,  G06T1/20

CPC classification number: G06F1/206 ,  G06F1/3206 ,  G06F1/3234 ,  G06F1/324 ,  G06F1/3296 ,  G06F11/3024 ,  G06F11/3058

Abstract: A three-dimensional (3-D) processor stack includes a plurality of processor cores implemented in a plurality of layers. A controller is to selectively throttle one or more of a plurality of processor cores in response to detecting a thermal event. The controller selectively throttles the one or more of the plurality of processor cores based on values of thermal couplings between the plurality of layers and based on measures of criticality of threads executing on the plurality of processor cores.

公开(公告)号：US10355966B2

公开(公告)日：2019-07-16

申请号：US15081558

申请日：2016-03-25

Applicant: Advanced Micro Devices, Inc.

Inventor： Samuel Lawrence Wasmundt ,  Leonardo Piga ,  Indrani Paul ,  Wei Huang ,  Manish Arora

IPC: H04L12/26 ,  H04L29/08

Abstract: Systems, apparatuses, and methods for managing variations among nodes in parallel system frameworks. Sensor and performance data associated with the nodes of a multi-node cluster may be monitored to detect variations among the nodes. A variability metric may be calculated for each node of the cluster based on the sensor and performance data associated with the node. The variability metrics may then be used by a mapper to efficiently map tasks of a parallel application to the nodes of the cluster. In one embodiment, the mapper may assign the critical tasks of the parallel application to the nodes with the lowest variability metrics. In another embodiment, the hardware of the nodes may be reconfigured so as to reduce the node-to-node variability.

公开(公告)号：US09990203B2

公开(公告)日：2018-06-05

申请号：US14981310

申请日：2015-12-28

Applicant: Advanced Micro Devices, Inc.

Inventor： Leonardo de Paula Rosa Piga ,  Abhinandan Majumdar ,  Indrani Paul ,  Wei Huang ,  Manish Arora ,  Joseph L. Greathouse

IPC: G06F9/30

CPC classification number: G06F9/30192 ,  G06F9/30014 ,  G06F9/30083 ,  G06F9/30145 ,  G06F11/00

Abstract: Methods, devices, and systems for capturing an accuracy of an instruction executing on a processor. An instruction may be executed on the processor, and the accuracy of the instruction may be captured using a hardware counter circuit. The accuracy of the instruction may be captured by analyzing bits of at least one value of the instruction to determine a minimum or maximum precision datatype for representing the field, and determining whether to adjust a value of the hardware counter circuit accordingly. The representation may be output to a debugger or logfile for use by a developer, or may be output to a runtime or virtual machine to automatically adjust instruction precision or gating of portions of the processor datapath.

公开(公告)号：US09921635B2

公开(公告)日：2018-03-20

申请号：US14068207

申请日：2013-10-31

Applicant: Advanced Micro Devices, Inc.

Inventor： Yasuko Eckert ,  Manish Arora

IPC: G06F1/32

CPC classification number: G06F1/3228 ,  G06F1/32 ,  G06F1/3203 ,  G06F1/3206 ,  G06F1/3231 ,  G06F1/324 ,  G06F1/3246 ,  Y02D10/126 ,  Y02D10/173

Abstract: An approach is described herein that includes a method for power management of a device. In one example, the method includes sampling duration characteristics for a plurality of past idle events for a predetermined interval of time and determining whether to transition a device to a powered-down state based on the sampled duration characteristics. In another example, the method includes determining whether an average idle time for a plurality of past idle events exceeds an energy break-even point threshold. If the average idle time for the plurality of past idle events exceeds the energy break-even point threshold, a device is immediately transitioned to a powered-down state upon receipt of a next idle event. If the average idle time for the plurality of past idle events does not exceed the energy break-even point threshold, transition of the device to the powered-down state is delayed.

公开(公告)号：US09851777B2

公开(公告)日：2017-12-26

申请号：US14146591

申请日：2014-01-02

Applicant: Advanced Micro Devices, Inc.

Inventor： Manish Arora ,  Indrani Paul ,  Yasuko Eckert ,  Nuwan S. Jayasena ,  Srilatha Manne ,  Madhu Saravana Sibi Govindan ,  William L. Bircher

IPC: G06F1/32

CPC classification number: G06F1/3287 ,  G06F1/3225 ,  Y02D10/171 ,  Y02D50/20

Abstract: Power gating decisions can be made based on measures of cache dirtiness. Analyzer logic can selectively power gate a component of a processor system based on a cache dirtiness of one or more caches associated with the component. The analyzer logic may power gate the component when the cache dirtiness exceeds a threshold and may maintains the component in an idle state when the cache dirtiness does not exceed the threshold. Idle time prediction logic may be used to predict a duration of an idle time of the component. The analyzer logic may then selectively power gates the component based on the cache dirtiness and the predicted idle time.

公开(公告)号：US09658663B2

公开(公告)日：2017-05-23

申请号：US14862044

申请日：2015-09-22

Applicant: Advanced Micro Devices, Inc.

Inventor： Wei Huang ,  Manish Arora ,  Yasuko Eckert ,  Indrani Paul

IPC: G06F1/28 ,  G06F1/30 ,  G06F1/20 ,  G06T1/20 ,  G06F1/32 ,  G06F11/30

CPC classification number: G06F1/206 ,  G06F1/3206 ,  G06F1/3234 ,  G06F1/324 ,  G06F1/3296 ,  G06F11/3024 ,  G06F11/3058

Abstract: A three-dimensional (3-D) processor stack includes a plurality of processor cores implemented in a plurality of layers. A controller is to selectively throttle one or more of a plurality of processor cores in response to detecting a thermal event. The controller selectively throttles the one or more of the plurality of processor cores based on values of thermal couplings between the plurality of layers and based on measures of criticality of threads executing on the plurality of processor cores.

公开(公告)号：US09471130B2

公开(公告)日：2016-10-18

申请号：US14063194

申请日：2013-10-25

Applicant: Advanced Micro Devices, Inc.

Inventor： Manish Arora ,  Nuwan S. Jayasena ,  Michael J. Schulte

IPC: G06F1/32

CPC classification number: G06F1/3228 ,  G06F1/3243 ,  G06F1/3287 ,  Y02D10/152 ,  Y02D10/171

Abstract: The described embodiments include a computing device with an entity (a processor, a processor core, etc.) and a controller. In these embodiments, the controller, using an idle duration history, predicts a duration of a next idle period for the entity. Based on the predicted duration of the next idle period, the controller configures the entity to operate in a corresponding idle state.

Abstract translation: 所描述的实施例包括具有实体（处理器，处理器核心等）和控制器的计算设备。 在这些实施例中，控制器使用空闲持续时间历史预测实体的下一个空闲时段的持续时间。 基于下一个空闲时段的预测持续时间，控制器将该实体配置为在相应的空闲状态下工作。