Flexible I/O partition of multi-die memory solution
Abstract:
A method of testing a microelectronic package configured to provide memory access can include energizing terminals of the microelectronic package, the terminals including first terminals configured to carry address information and second terminals configured to carry data signals. The method can also include applying read and write test data signals simultaneously to the first and second sets of second terminals, so as to simultaneously test read and write operation in first and second microelectronic elements of the microelectronic package. The first and second microelectronic elements can be configured to provide access to memory storage array locations in the first and second microelectronic elements. The terminals can also include third terminals configured to receive a test mode input that reconfigures the first and second microelectronic elements to permit simultaneous access to memory storage array locations in the first and second microelectronic elements.
Information query
Patent Agency Ranking
0/0