Invention Grant
- Patent Title: Semiconductor device with bond pad wiring lead-out arrangement avoiding bond pad probe mark area
-
Application No.: US15219254Application Date: 2016-07-25
-
Publication No.: US09646901B2Publication Date: 2017-05-09
- Inventor: Toshihiko Akiba , Bunji Yasumura , Masanao Sato , Hiromi Abe
- Applicant: Renesas Electronics Corporation
- Applicant Address: JP Tokyo
- Assignee: Renesas Electronics Corporation
- Current Assignee: Renesas Electronics Corporation
- Current Assignee Address: JP Tokyo
- Agency: Shapiro, Gabor and Rosenberger, PLLC
- Priority: JP2008-092633 20080331
- Main IPC: H01L23/58
- IPC: H01L23/58 ; H01L21/66 ; H01L23/00 ; H01L25/065 ; G01R31/26

Abstract:
Provided is a semiconductor device having a pad on a semiconductor chip, a first passivation film formed over the semiconductor chip and having an opening portion on the pad of a probe region and a coupling region, a second passivation film formed over the pad and the first passivation film and having an opening portion on the pad of the coupling region, and a rewiring layer formed over the coupling region and the second passivation film and electrically coupled to the pad. The pad of the probe region placed on the periphery side of the semiconductor chip relative to the coupling region has a probe mark and the rewiring layer extends from the coupling region to the center side of the semiconductor chip. The present invention provides a technology capable of achieving size reduction, particularly pitch narrowing, of a semiconductor device.
Public/Granted literature
- US20160336244A1 SEMICONDUCTOR DEVICE Public/Granted day:2016-11-17
Information query
IPC分类: