Method for manufacturing semiconductor device

    公开(公告)号:US10141295B2

    公开(公告)日:2018-11-27

    申请号:US15730977

    申请日:2017-10-12

    摘要: To improve the assemblability of a semiconductor device.When a memory chip is mounted over a logic chip, a recognition range including a recognition mark formed at a back surface of the logic chip is imaged and a shape of the recognition range is recognized, alignment of a plurality of bumps of the logic chip and a plurality of projection electrodes of the above-described memory chip is performed based on a result of the recognition, and the above-described memory chip is mounted over the logic chip. At this time, the shape of the recognition range is different from any portion of an array shape of the bumps, as a result, the recognition mark in the shape of the recognition range can be reliably recognized, and alignment of the bumps of the logic chip and the projection electrodes of the above-described memory chip is performed with high accuracy.

    MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE

    公开(公告)号:US20190057913A1

    公开(公告)日:2019-02-21

    申请号:US16167492

    申请日:2018-10-22

    摘要: Provided is a semiconductor device having a pad on a semiconductor chip, a first passivation film formed over the semiconductor chip and having an opening portion on the pad of a probe region and a coupling region, a second passivation film formed over the pad and the first passivation film and having an opening portion on the pad of the coupling region, and a rewiring layer formed over the coupling region and the second passivation film and electrically coupled to the pad. The pad of the probe region placed on the periphery side of the semiconductor chip relative to the coupling region has a probe mark and the rewiring layer extends from the coupling region to the center side of the semiconductor chip. The present invention provides a technology capable of achieving size reduction, particularly pitch narrowing, of a semiconductor device.

    Method of manufacturing semiconductor device

    公开(公告)号:US10566255B2

    公开(公告)日:2020-02-18

    申请号:US16519150

    申请日:2019-07-23

    摘要: Provided is a semiconductor device having a pad on a semiconductor chip, a first passivation film formed over the semiconductor chip and having an opening portion on the pad of a probe region and a coupling region, a second passivation film formed over the pad and the first passivation film and having an opening portion on the pad of the coupling region, and a rewiring layer formed over the coupling region and the second passivation film and electrically coupled to the pad. The pad of the probe region placed on the periphery side of the semiconductor chip relative to the coupling region has a probe mark and the rewiring layer extends from the coupling region to the center side of the semiconductor chip. The present invention provides a technology capable of achieving size reduction, particularly pitch narrowing, of a semiconductor device.

    Semiconductor device
    9.
    发明授权

    公开(公告)号:US10163740B2

    公开(公告)日:2018-12-25

    申请号:US15785531

    申请日:2017-10-17

    摘要: A technique is provided that can prevent cracking of a protective film in the uppermost layer of a semiconductor device and improve the reliability of the semiconductor device. Bonding pads formed over a principal surface of a semiconductor chip are in a rectangular shape, and an opening is formed in a protective film over each bonding pad in such a manner that an overlapping width of the protective film in a wire bonding region of each bonding pad becomes wider than an overlapping width of the protective film in a probe region of each bonding pad.