Invention Grant
- Patent Title: Low leakage gate controlled vertical electrostatic discharge protection device integration with a planar FinFET
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Application No.: US15285985Application Date: 2016-10-05
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Publication No.: US09646962B1Publication Date: 2017-05-09
- Inventor: Qing Liu , Ruilong Xie , Chun-chen Yeh
- Applicant: International Business Machines Corporation , GLOBALFOUNDRIES INC. , STMICROELECTRONICS, INC.
- Applicant Address: US NY Armonk US TX Coppell KY Grand Cayman
- Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION,STMICROELECTRONICS, INC.,GLOBALFOUNDRIES INC.
- Current Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION,STMICROELECTRONICS, INC.,GLOBALFOUNDRIES INC.
- Current Assignee Address: US NY Armonk US TX Coppell KY Grand Cayman
- Agency: Cantor Colburn LLP
- Agent Vazken Alexanian
- Main IPC: H01L27/02
- IPC: H01L27/02 ; H01L27/092 ; H01L29/861 ; H01L29/66 ; H01L21/8238 ; H01L29/06 ; H01L29/10

Abstract:
A semiconductor device includes an electrostatic discharge (ESD) device formed adjacent to a first fin field effect transistor (finFET). The device includes a substrate, the first finFET and the ESD device. The first finFET is formed such that it includes finFET fins extending from the substrate. The ESD device includes two vertically stacked PN diodes including vertically stacked first, second, third and fourth layers. The first layer is an N doped layer and is disposed directly over the substrate, the second layer is a P doped layer and is disposed directly over the first layer, the third layer is an N doped layer and is disposed directly over the second layer and the fourth layer is a P doped layer and is disposed directly over the third layer.
Information query
IPC分类: