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公开(公告)号：US10276573B2
公开(公告)日：2019-04-30
申请号：US15168382
申请日：2016-05-31
发明人： Xiuyu Cai , Qing Liu , Ruilong Xie , Chun-chen Yeh
IPC分类号： H01L27/092 , H01L21/8238 , H01L29/16 , H01L29/06 , H01L21/308 , H01L21/033 , H01L29/78 , H01L29/165 , H01L21/84 , H01L27/12 , H01L29/10
摘要： A semiconductor substrate includes a bulk substrate layer that extends along a first axis to define a width and a second axis perpendicular to the first axis to define a height. A plurality of hetero semiconductor fins includes an epitaxial material formed on a first region of the bulk substrate layer. A plurality of non-hetero semiconductor fins is formed on a second region of the bulk substrate layer different from the first region. The non-hetero semiconductor fins are integrally formed from the bulk substrate layer such that the material of the non-hetero semiconductor fins is different from the epitaxial material.
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公开(公告)号：US09887196B2
公开(公告)日：2018-02-06
申请号：US14583842
申请日：2014-12-29
发明人： Xiuyu Cai , Qing Liu , Ruilong Xie , Chun-chen Yeh
IPC分类号： H01L27/092 , H01L29/10 , H01L27/12 , H01L21/84 , H01L29/165 , H01L21/308 , H01L21/8238 , H01L29/16 , H01L29/06 , H01L21/033 , H01L29/78
CPC分类号： H01L27/0924 , H01L21/0338 , H01L21/3086 , H01L21/3088 , H01L21/823807 , H01L21/823821 , H01L21/845 , H01L27/0922 , H01L27/1211 , H01L29/0684 , H01L29/1054 , H01L29/16 , H01L29/165 , H01L29/7849
摘要： A semiconductor substrate includes a bulk substrate layer that extends along a first axis to define a width and a second axis perpendicular to the first axis to define a height. A plurality of hetero semiconductor fins includes an epitaxial material formed on a first region of the bulk substrate layer. A plurality of non-hetero semiconductor fins is formed on a second region of the bulk substrate layer different from the first region. The non-hetero semiconductor fins are integrally formed from the bulk substrate layer such that the material of the non-hetero semiconductor fins is different from the epitaxial material.
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公开(公告)号：US09685555B2
公开(公告)日：2017-06-20
申请号：US14584161
申请日：2014-12-29
发明人： Qing Liu , Nicolas Loubet , Chun-chen Yeh , Ruilong Xie , Xiuyu Cai
IPC分类号： H01L29/49 , H01L29/78 , H01L29/66 , H01L29/06 , H01L21/768
CPC分类号： H01L29/7856 , H01L21/76816 , H01L21/76897 , H01L29/0657 , H01L29/4975 , H01L29/6681 , H01L2029/7858
摘要： Tapered source and drain contacts for use in an epitaxial FinFET prevent short circuits and damage to parts of the FinFET during contact processing, thus improving device reliability. The inventive contacts feature tapered sidewalls and a pedestal where electrical contact is made to fins in the source and drain regions. The pedestal also provides greater contact area to the fins, which are augmented by extensions. Raised isolation regions define a valley around the fins. During source/drain contact formation, the valley is lined with a conformal barrier that also covers the fins themselves. The barrier protects underlying local oxide and adjacent isolation regions against gouging while forming the contact. The valley is filled with an amorphous silicon layer that protects the epitaxial fin material from damage during contact formation. A simple tapered structure is used for the gate contact.
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4.发明授权Method for making a semiconductor device with sidewall spacers for confining epitaxial growth 有权制造具有用于限制外延生长的侧壁间隔物的半导体器件的方法公开(公告)号：US09431540B2
公开(公告)日：2016-08-30
申请号：US14288766
申请日：2014-05-28
发明人： Qing Liu , Ruilong Xie , Xiuyu Cai , Chun-chen Yeh
IPC分类号： H01L29/66 , H01L29/165 , H01L29/78
CPC分类号： H01L29/66795 , H01L21/02164 , H01L21/02178 , H01L21/0228 , H01L21/31105 , H01L21/823814 , H01L21/823821 , H01L27/0924 , H01L29/0847 , H01L29/1033 , H01L29/165 , H01L29/785 , H01L29/7851
摘要： A method for making a semiconductor device includes forming laterally spaced-apart semiconductor fins above a substrate. At least one dielectric layer is formed adjacent an end portion of the semiconductor fins and within the space between adjacent semiconductor fins. A pair of sidewall spacers is formed adjacent outermost semiconductor fins at the end portion of the semiconductor fins. The at least one dielectric layer and end portion of the semiconductor fins between the pair of sidewall spacers are removed. Source/drain regions are formed between the pair of sidewall spacers.
摘要翻译： 制造半导体器件的方法包括在衬底上形成横向间隔开的半导体鳍片。 在半导体鳍片的端部附近和相邻的半导体鳍片之间的空间内形成至少一个电介质层。 在半导体翅片的端部处邻近最外半导体翅片形成一对侧壁间隔物。 去除该对侧壁间隔物之间的至少一个电介质层和半导体翅片的端部。 源极/漏极区域形成在该对侧壁间隔物之间。
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公开(公告)号：US09406751B2
公开(公告)日：2016-08-02
申请号：US14296818
申请日：2014-06-05
发明人： Qing Liu , Xiuyu Cai , Ruilong Xie , Chun-chen Yeh
IPC分类号： H01L29/08 , H01L27/12 , H01L29/786 , H01L21/84 , H01L21/8238
CPC分类号： H01L21/823807 , H01L21/76895 , H01L21/823814 , H01L21/823871 , H01L21/823878 , H01L21/84 , H01L27/1203 , H01L29/0847 , H01L29/7842 , H01L29/7848 , H01L29/786 , H01L29/78684
摘要： A method for making a semiconductor device is provided. Raised source and drain regions are formed with a tensile strain-inducing material, after thermal treatment to form source drain extension regions, to thereby preserve the strain-inducing material in desired substitutional states.
摘要翻译： 提供一种制造半导体器件的方法。 在热处理之后，用拉伸应变诱导材料形成凸起的源极和漏极区域以形成源极漏极延伸区域，从而将应变诱导材料保持在期望的替代状态。
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公开(公告)号：US20150380258A1
公开(公告)日：2015-12-31
申请号：US14314384
申请日：2014-06-25
发明人： Qing Liu , Ruilong Xie , Xiuyu Cai , Chun-chen Yeh , Kejia Wang
IPC分类号： H01L21/308 , H01L29/205 , H01L29/78
CPC分类号： H01L29/205 , H01L29/1054 , H01L29/66795 , H01L29/785
摘要： Methods and structures for forming fin structures whilst controlling the height of the fin structures with high uniformity across large areas are described. According to some aspects, a multi-layer structure comprising a first etch-stop layer and a second etch-stop layer separated from a substrate and from each other by spacer layers is formed on a substrate. Trenches may be formed through the first and second etch-stop layers. A buffer layer may be formed in the trenches, filling the trenches to a level approximately at a position of the first etch-stop layer. A semiconductor layer may be formed above the buffer layer and etched back to the second etch-stop layer to form semiconductor fins of highly uniform heights.
摘要翻译： 描述了形成翅片结构的方法和结构，同时在大面积上以高均匀性控制翅片结构的高度。 根据一些方面，在衬底上形成包括由衬底分离并通过间隔层彼此分离的第一蚀刻停止层和第二蚀刻停止层的多层结构。 沟槽可以通过第一和第二蚀刻停止层形成。 可以在沟槽中形成缓冲层，将沟槽填充到大致在第一蚀刻停止层的位置处的水平。 半导体层可以形成在缓冲层的上方并被回蚀刻到第二蚀刻停止层以形成高均匀高度的半导体鳍片。
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7.发明授权公开(公告)号：US09202920B1
公开(公告)日：2015-12-01
申请号：US14447727
申请日：2014-07-31
发明人： Qing Liu , Chun-chen Yeh , Ruilong Xie , Xiuyu Cai
CPC分类号： H01L29/785 , H01L29/66553 , H01L29/66795 , H01L29/7848
摘要： Methods and structures for forming short-channel finFETs with vertical and abrupt source and drain junctions are described. During fabrication, source and drain regions of the finFET may be recessed vertically and laterally under gate spacers. A buffer having a high dopant density may be formed on vertical sidewalls of the channel region after recessing the fin. Raised source and drain structures may be formed at the recessed source and drain regions. The raised source and drain structures may impart strain to the channel region.
摘要翻译： 描述了用于形成具有垂直和突然的源极和漏极结的短沟道finFET的方法和结构。 在制造期间，finFET的源极和漏极区域可以在栅极间隔物下方垂直和横向地凹陷。 具有高掺杂浓度的缓冲器可以在凹陷鳍片之后形成在沟道区域的垂直侧壁上。 可以在凹陷的源极和漏极区域形成升高的源极和漏极结构。 升高的源极和漏极结构可能对沟道区域施加应变。
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8.发明授权公开(公告)号：US10290636B2
公开(公告)日：2019-05-14
申请号：US14461769
申请日：2014-08-18
发明人： Qing Liu , Chun-chen Yeh , Ruilong Xie , Xiuyu Cai
IPC分类号： H01L27/092 , H01L29/167 , H01L29/161 , H01L29/10 , H01L21/8238 , H01L21/265 , H01L29/06
摘要： A method for making a semiconductor device may include forming first and second semiconductor regions laterally adjacent one another and each comprising a first semiconductor material. The method may further include forming an in-situ doped, punch-through stopper layer above the second semiconductor region comprising the first semiconductor material and a first dopant, and forming a semiconductor buffer layer above the punch-through stopper layer, where the punch-through stopper layer includes the first semiconductor material. The method may also include forming a third semiconductor region above the semiconductor buffer layer, where the third semiconductor region includes a second semiconductor material different than the first semiconductor material. In addition, at least one first fin may be formed from the first semiconductor region, and at least one second fin may be formed from the second semiconductor region, the punch-through stopper layer, the semiconductor buffer layer, and the third semiconductor region.
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公开(公告)号：US20180102433A1
公开(公告)日：2018-04-12
申请号：US15693952
申请日：2017-09-01
发明人： Qing Liu , Ruilong Xie , Chun-chen Yeh
IPC分类号： H01L29/78 , H01L29/417 , H01L21/324 , H01L21/02 , H01L21/306 , H01L29/66
CPC分类号： H01L29/7827 , H01L21/02614 , H01L21/30604 , H01L21/324 , H01L29/41741 , H01L29/66553 , H01L29/66666
摘要： A method of fabricating features of a vertical transistor include performing a first etch process to form a first portion of a fin in a substrate; depositing a spacer material on sidewalls of the first portion of the fin; performing a second etch process using the spacer material as a pattern to elongate the fin and form a second portion of the fin in the substrate, the second portion having a width that is greater than the first portion; oxidizing a region of the second portion of the fin beneath the spacer material to form an oxidized channel region; and removing the oxidized channel region to form a vacuum channel.
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10.发明申请公开(公告)号：US20160293761A1
公开(公告)日：2016-10-06
申请号：US15180860
申请日：2016-06-13
发明人： Qing Liu , Xiuyu Cai , Ruilong Xie , Chun-chen Yeh
IPC分类号： H01L29/78 , H01L29/161 , H01L27/12 , H01L29/165 , H01L29/10 , H01L29/06 , H01L29/08 , H01L29/16
CPC分类号： H01L27/1211 , G06N3/04 , G10L15/16 , H01L21/28132 , H01L21/823437 , H01L21/823468 , H01L29/0649 , H01L29/1037 , H01L29/365 , H01L29/41775 , H01L29/41783 , H01L29/41791 , H01L29/66553 , H01L29/66636 , H01L29/66795 , H01L29/7848 , H01L29/785 , H01L2029/7858 , H01L2924/13067
摘要： Techniques and structures for controlling etch-back of a finFET fin are described. One or more layers may be deposited over the fin and etched. Etch-back of a planarization layer may be used to determine a self-limited etch height of one or more layers adjacent the fin and a self-limited etch height of the fin. Strain-inducing material may be formed at regions of the etched fin to induce strain in the channel of a finFET.
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