Invention Grant
- Patent Title: Interconnect structure having large self-aligned vias
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Application No.: US14231448Application Date: 2014-03-31
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Publication No.: US09658523B2Publication Date: 2017-05-23
- Inventor: John H. Zhang , Lawrence A. Clevenger , Carl Radens , Yiheng Xu , Richard Stephen Wise , Terry Spooner , Nicole A. Saulnier
- Applicant: STMicroelectronics, Inc. , International Business Machines Corporation
- Applicant Address: US TX Coppell US NY Armonk
- Assignee: STMicroelectronics, Inc.,International Business Machines Corporation
- Current Assignee: STMicroelectronics, Inc.,International Business Machines Corporation
- Current Assignee Address: US TX Coppell US NY Armonk
- Agency: Seed IP Law Group LLP
- Main IPC: G03F1/36
- IPC: G03F1/36 ; H01L21/768 ; H01L23/522 ; H01L23/528 ; H01L21/027 ; H01L21/311

Abstract:
A wavy line interconnect structure that accommodates small metal lines and large vias is disclosed. A lithography mask design used to pattern metal line trenches uses optical proximity correction (OPC) techniques to approximate wavy lines using rectangular opaque features. The large vias can be formed using a self-aligned dual damascene process without the need for a separate via lithography mask. Instead, a sacrificial layer allows etching of an underlying thick dielectric block, while protecting narrow features of the trenches that correspond to the metal line interconnects. The resulting vias have an aspect ratio that is relatively easy to fill, while the larger via footprint provides low via resistance. By lifting the shrink constraint for vias, thereby allowing the via footprint to exceed the minimum size of the metal line width, a path is cleared for further process generations to continue shrinking metal lines to dimensions below 10 nm.
Public/Granted literature
- US20150279784A1 INTERCONNECT STRUCTURE HAVING LARGE SELF-ALIGNED VIAS Public/Granted day:2015-10-01
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