Invention Grant
- Patent Title: Forming barrier walls, capping, or alloys /compounds within metal lines
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Application No.: US13630724Application Date: 2012-09-28
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Publication No.: US09659869B2Publication Date: 2017-05-23
- Inventor: Christopher J Jezewski , Alan M Meyers , Kanwal Jit Singh , Tejaswi K Indukuri , James S Clarke , Florian Gstrein
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Forefront IP Lawgroup, PLLC
- Main IPC: H01L23/532
- IPC: H01L23/532 ; H01L21/768
Abstract:
Described herein are techniques structures related to forming barrier walls, capping, or alloys/compounds such as treating copper so that an alloy or compound is formed, to reduce electromigration (EM) and strengthen metal reliability which degrades as the length of the lines increases in integrated circuits.
Public/Granted literature
- US20140091467A1 FORMING BARRIER WALLS, CAPPING, OR ALLOYS /COMPOUNDS WITHIN METAL LINES Public/Granted day:2014-04-03
Information query
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