公开(公告)号：US09659869B2

公开(公告)日：2017-05-23

申请号：US13630724

申请日：2012-09-28

Applicant: Intel Corporation

Inventor： Christopher J Jezewski ,  Alan M Meyers ,  Kanwal Jit Singh ,  Tejaswi K Indukuri ,  James S Clarke ,  Florian Gstrein

IPC: H01L23/532 ,  H01L21/768

CPC classification number: H01L23/53238 ,  H01L21/76808 ,  H01L21/76843 ,  H01L21/76847 ,  H01L21/76849 ,  H01L21/76883 ,  H01L21/76886 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Described herein are techniques structures related to forming barrier walls, capping, or alloys/compounds such as treating copper so that an alloy or compound is formed, to reduce electromigration (EM) and strengthen metal reliability which degrades as the length of the lines increases in integrated circuits.