Invention Grant
- Patent Title: Method for making semiconductor device with stacked analog components in back end of line (BEOL) regions
-
Application No.: US15082987Application Date: 2016-03-28
-
Publication No.: US09660015B2Publication Date: 2017-05-23
- Inventor: John H. Zhang
- Applicant: STMicroelectronics, Inc.
- Applicant Address: US TX Coppell
- Assignee: STMicroelectronics, Inc.
- Current Assignee: STMicroelectronics, Inc.
- Current Assignee Address: US TX Coppell
- Agency: Seed IP Law Group LLP
- Main IPC: H01L49/02
- IPC: H01L49/02 ; H01L21/768 ; H01L23/522 ; H01L27/06 ; H01L27/08 ; H01L23/528 ; H01L23/532

Abstract:
A method for making a semiconductor device may include forming a first dielectric layer above a semiconductor substrate, forming a first trench in the first dielectric layer, filling the first trench with electrically conductive material, removing upper portions of the electrically conductive material to define a lower conductive member with a recess thereabove, forming a filler dielectric material in the recess to define a second trench. The method may further include filling the second trench with electrically conductive material to define an upper conductive member, forming a second dielectric layer over the first dielectric layer and upper conductive member, forming a first via through the second dielectric layer and underlying filler dielectric material to the lower conductive member, and forming a second via through the second dielectric layer to the upper conductive member.
Public/Granted literature
- US20160254343A1 METHOD FOR MAKING SEMICONDUCTOR DEVICE WITH STACKED ANALOG COMPONENTS IN BACK END OF LINE (BEOL) REGIONS Public/Granted day:2016-09-01
Information query
IPC分类: